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Only implement one solution for native triggers. #1793

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merged 4 commits into from
Sep 10, 2024
Merged

Only implement one solution for native triggers. #1793

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9c5a20f
Work if tcontrol doesn't exist.
rtwfroody Sep 5, 2024
4abd669
Make allow_action() take proc instead of state
rtwfroody Sep 5, 2024
451a7dc
triggers: Move allow_action() into common_match()
rtwfroody Sep 9, 2024
0703b44
Only implement one solution for native triggers.
rtwfroody Sep 5, 2024
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5 changes: 3 additions & 2 deletions riscv/csr_init.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -205,13 +205,14 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
add_csr(CSR_TDATA2, tdata2 = std::make_shared<tdata2_csr_t>(proc, CSR_TDATA2));
add_csr(CSR_TDATA3, std::make_shared<tdata3_csr_t>(proc, CSR_TDATA3));
add_csr(CSR_TINFO, std::make_shared<tinfo_csr_t>(proc, CSR_TINFO));
add_csr(CSR_TCONTROL, tcontrol = std::make_shared<masked_csr_t>(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0));
if (!proc->extension_enabled_const('S')) {
add_csr(CSR_TCONTROL, tcontrol = std::make_shared<masked_csr_t>(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0));
}
} else {
add_csr(CSR_TDATA1, std::make_shared<const_csr_t>(proc, CSR_TDATA1, 0));
add_csr(CSR_TDATA2, tdata2 = std::make_shared<const_csr_t>(proc, CSR_TDATA2, 0));
add_csr(CSR_TDATA3, std::make_shared<const_csr_t>(proc, CSR_TDATA3, 0));
add_csr(CSR_TINFO, std::make_shared<const_csr_t>(proc, CSR_TINFO, 0));
add_csr(CSR_TCONTROL, tcontrol = std::make_shared<const_csr_t>(proc, CSR_TCONTROL, 0));
}
unsigned scontext_length = (xlen == 32 ? 16 : 32); // debug spec suggests 16-bit for RV32 and 32-bit for RV64
add_supervisor_csr(CSR_SCONTEXT, scontext = std::make_shared<masked_csr_t>(proc, CSR_SCONTEXT, (reg_t(1) << scontext_length) - 1, 0));
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2 changes: 1 addition & 1 deletion riscv/insns/mret.h
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Expand Up @@ -20,5 +20,5 @@ if (prev_virt && prev_prv == PRV_U)
STATE.vsstatus->write(STATE.vsstatus->read() & ~SSTATUS_SDT);
STATE.mstatus->write(s);
if (STATE.mstatush) STATE.mstatush->write(s >> 32); // log mstatush change
STATE.tcontrol->write((STATE.tcontrol->read() & CSR_TCONTROL_MPTE) ? (CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE) : 0);
if (STATE.tcontrol) STATE.tcontrol->write((STATE.tcontrol->read() & CSR_TCONTROL_MPTE) ? (CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE) : 0);
p->set_privilege(prev_prv, prev_virt);
2 changes: 1 addition & 1 deletion riscv/processor.cc
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Expand Up @@ -535,7 +535,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
state.elp = elp_t::NO_LP_EXPECTED;
state.mstatus->write(s);
if (state.mstatush) state.mstatush->write(s >> 32); // log mstatush change
state.tcontrol->write((state.tcontrol->read() & CSR_TCONTROL_MTE) ? CSR_TCONTROL_MPTE : 0);
if (state.tcontrol) state.tcontrol->write((state.tcontrol->read() & CSR_TCONTROL_MTE) ? CSR_TCONTROL_MPTE : 0);
set_privilege(PRV_M, false);
}
}
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69 changes: 48 additions & 21 deletions riscv/triggers.cc
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Expand Up @@ -55,12 +55,54 @@ void trigger_t::tdata3_write(processor_t * const proc, const reg_t val) noexcept
sselect = (sselect_t)((proc->extension_enabled_const('S') && get_field(val, CSR_TEXTRA_SSELECT(xlen)) <= SSELECT_MAXVAL) ? get_field(val, CSR_TEXTRA_SSELECT(xlen)) : SSELECT_IGNORE);
}

static reg_t tcontrol_value(const state_t * state) {
if (state->tcontrol)
return state->tcontrol->read();
else
return 0;
}

bool trigger_t::common_match(processor_t * const proc, bool use_prev_prv) const noexcept {
auto state = proc->get_state();
auto prv = use_prev_prv ? state->prev_prv : state->prv;
auto v = use_prev_prv ? state->prev_v : state->v;
auto m_enabled = get_action() != 0 || (state->tcontrol->read() & CSR_TCONTROL_MTE);
return (prv < PRV_M || m_enabled) && mode_match(prv, v) && textra_match(proc);

if (!mode_match(prv, v))
return false;

if (!textra_match(proc))
return false;

if (get_action() == ACTION_DEBUG_EXCEPTION) {
if (proc->extension_enabled('S')) {
// The hardware prevents triggers with action=0 from matching or firing
// while in M-mode and while MIE in mstatus is 0. If medeleg [3]=1 then it
// prevents triggers with action=0 from matching or firing while in S-mode
// and while SIE in sstatus is 0. If medeleg [3]=1 and hedeleg [3]=1 then
// it prevents triggers with action=0 from matching or firing while in
// VS-mode and while SIE in vstatus is 0.

const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE;
if (prv == PRV_M && !mstatus_mie)
return false;

const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE;
const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1;
if (prv == PRV_S && !v && medeleg_breakpoint && !sstatus_sie)
return false;

const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE;
const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1;
if (prv == PRV_S && v && medeleg_breakpoint && hedeleg_breakpoint && !vsstatus_sie)
return false;
} else {
// mte and mpte in tcontrol is implemented. medeleg [3] is hard-wired to 0.
if (prv == PRV_M && !(tcontrol_value(state) & CSR_TCONTROL_MTE))
return false;
}
}

return true;
}

bool trigger_t::mode_match(reg_t prv, bool v) const noexcept
Expand Down Expand Up @@ -110,21 +152,6 @@ bool trigger_t::textra_match(processor_t * const proc) const noexcept
return true;
}

bool trigger_t::allow_action(const state_t * const state) const
{
if (get_action() == ACTION_DEBUG_EXCEPTION) {
const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE;
const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE;
const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE;
const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1;
const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1;
return (state->prv != PRV_M || mstatus_mie) &&
(state->prv != PRV_S || state->v || !medeleg_breakpoint || sstatus_sie) &&
(state->prv != PRV_S || !state->v || !medeleg_breakpoint || !hedeleg_breakpoint || vsstatus_sie);
}
return true;
}

reg_t disabled_trigger_t::tdata1_read(const processor_t * const proc) const noexcept
{
auto xlen = proc->get_xlen();
Expand Down Expand Up @@ -235,7 +262,7 @@ std::optional<match_result_t> mcontrol_common_t::detect_memory_access_match(proc
value &= 0xffffffff;
}

if (simple_match(xlen, value) && allow_action(proc->get_state())) {
if (simple_match(xlen, value)) {
/* This is OK because this function is only called if the trigger was not
* inhibited by the previous trigger in the chain. */
set_hit(timing ? HIT_IMMEDIATELY_AFTER : HIT_BEFORE);
Expand Down Expand Up @@ -324,7 +351,7 @@ void mcontrol6_t::tdata1_write(processor_t * const proc, const reg_t val, const

std::optional<match_result_t> icount_t::detect_icount_fire(processor_t * const proc) noexcept
{
if (!common_match(proc) || !allow_action(proc->get_state()))
if (!common_match(proc))
return std::nullopt;

std::optional<match_result_t> ret = std::nullopt;
Expand All @@ -339,7 +366,7 @@ std::optional<match_result_t> icount_t::detect_icount_fire(processor_t * const p

void icount_t::detect_icount_decrement(processor_t * const proc) noexcept
{
if (!common_match(proc) || !allow_action(proc->get_state()))
if (!common_match(proc))
return;

if (count >= 1) {
Expand Down Expand Up @@ -431,7 +458,7 @@ std::optional<match_result_t> trap_common_t::detect_trap_match(processor_t * con
bool interrupt = (t.cause() & ((reg_t)1 << (xlen - 1))) != 0;
reg_t bit = t.cause() & ~((reg_t)1 << (xlen - 1));
assert(bit < xlen);
if (simple_match(interrupt, bit) && allow_action(proc->get_state())) {
if (simple_match(interrupt, bit)) {
hit = true;
return match_result_t(TIMING_AFTER, action);
}
Expand Down
1 change: 0 additions & 1 deletion riscv/triggers.h
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Expand Up @@ -99,7 +99,6 @@ class trigger_t {
protected:
static action_t legalize_action(reg_t val, reg_t action_mask, reg_t dmode_mask) noexcept;
bool common_match(processor_t * const proc, bool use_prev_prv = false) const noexcept;
bool allow_action(const state_t * const state) const;
reg_t tdata2;

bool vs = false;
Expand Down
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