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[vector-crypto] Fixing Zvkb/Zvbb distinction #1474

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[vector-crypto] Fixing Zvkb/Zvbb distinction #1474

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9cddf20
[vector-crypto] Fixing Zvkb/Zvbb distinction
nibrunie Sep 29, 2023
f94914f
Fixing space -> tab in riscv.mk.in
nibrunieAtSi5 Sep 30, 2023
71a5ef4
fixing ZVBB -> ZVKB in isa_parser aliases
nibrunie Oct 1, 2023
d851b90
fixing enabling EXT_ZVBB+EXT_ZVKB when zvbb enabled
nibrunie Oct 1, 2023
3180edd
fixing disasm split ZVKB/ZVBB
nibrunie Oct 1, 2023
6a31dc2
Update disasm/disasm.cc
nibrunieAtSi5 Oct 2, 2023
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27 changes: 16 additions & 11 deletions disasm/disasm.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2125,38 +2125,43 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
DEFINE_R1TYPE(sm3p1);
}

if (isa->extension_enabled(EXT_ZVBB)) {
if (isa->extension_enabled(EXT_ZVKB)) {
#define DEFINE_VECTOR_VIU_ZIMM6(code) \
add_vector_viu_z6_insn(this, #code, match_##code, mask_##code)
#define DISASM_VECTOR_VV_VX(name) \
DEFINE_VECTOR_VV(name##_vv); \
DEFINE_VECTOR_VX(name##_vx)
#define DISASM_VECTOR_VV_VX_VIU(name) \
DEFINE_VECTOR_VV(name##_vv); \
DEFINE_VECTOR_VX(name##_vx); \
DEFINE_VECTOR_VIU(name##_vi)
#define DISASM_VECTOR_VV_VX_VIU_ZIMM6(name) \
DEFINE_VECTOR_VV(name##_vv); \
DEFINE_VECTOR_VX(name##_vx); \
DEFINE_VECTOR_VIU_ZIMM6(name##_vi)

DISASM_VECTOR_VV_VX(vandn);
DEFINE_VECTOR_V(vbrev_v);
DEFINE_VECTOR_V(vbrev8_v);
DEFINE_VECTOR_V(vrev8_v);
DEFINE_VECTOR_V(vclz_v);
DEFINE_VECTOR_V(vctz_v);
DEFINE_VECTOR_V(vcpop_v);
DISASM_VECTOR_VV_VX(vrol);
DISASM_VECTOR_VV_VX_VIU_ZIMM6(vror);
DISASM_VECTOR_VV_VX_VIU(vwsll);

#undef DEFINE_VECTOR_VIU_ZIMM6
#undef DISASM_VECTOR_VV_VX
#undef DISASM_VECTOR_VV_VX_VIU
#undef DISASM_VECTOR_VV_VX_VIU_ZIMM6
}

if (isa->extension_enabled(EXT_ZVBB)) {
#define DISASM_VECTOR_VV_VX_VIU(name) \
DEFINE_VECTOR_VV(name##_vv); \
DEFINE_VECTOR_VX(name##_vx); \
DEFINE_VECTOR_VIU(name##_vi)

DEFINE_VECTOR_V(vbrev_v);
DEFINE_VECTOR_V(vclz_v);
DEFINE_VECTOR_V(vctz_v);
DEFINE_VECTOR_V(vcpop_v);
DISASM_VECTOR_VV_VX_VIU(vwsll);

#undef DISASM_VECTOR_VV_VX_VIU
}

if (isa->extension_enabled(EXT_ZVBC)) {
#define DISASM_VECTOR_VV_VX(name) \
DEFINE_VECTOR_VV(name##_vv); \
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15 changes: 9 additions & 6 deletions disasm/isa_parser.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -251,25 +251,28 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
extension_table[EXT_ZCMLSD] = true;
} else if (ext_str == "zvbb") {
extension_table[EXT_ZVBB] = true;
extension_table[EXT_ZVKB] = true;
} else if (ext_str == "zvbc") {
extension_table[EXT_ZVBC] = true;
} else if (ext_str == "zvfbfmin") {
extension_table[EXT_ZVFBFMIN] = true;
} else if (ext_str == "zvfbfwma") {
extension_table[EXT_ZVFBFWMA] = true;
} else if (ext_str == "zvkb") {
extension_table[EXT_ZVKB] = true;
} else if (ext_str == "zvkg") {
extension_table[EXT_ZVKG] = true;
} else if (ext_str == "zvkn") {
extension_table[EXT_ZVBB] = true;
extension_table[EXT_ZVKB] = true;
extension_table[EXT_ZVKNED] = true;
extension_table[EXT_ZVKNHB] = true;
} else if (ext_str == "zvknc") {
extension_table[EXT_ZVBB] = true;
extension_table[EXT_ZVKB] = true;
extension_table[EXT_ZVBC] = true;
extension_table[EXT_ZVKNED] = true;
extension_table[EXT_ZVKNHB] = true;
} else if (ext_str == "zvkng") {
extension_table[EXT_ZVBB] = true;
extension_table[EXT_ZVKB] = true;
extension_table[EXT_ZVKG] = true;
extension_table[EXT_ZVKNED] = true;
extension_table[EXT_ZVKNHB] = true;
Expand All @@ -280,16 +283,16 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
} else if (ext_str == "zvknhb") {
extension_table[EXT_ZVKNHB] = true;
} else if (ext_str == "zvks") {
extension_table[EXT_ZVBB] = true;
extension_table[EXT_ZVKB] = true;
extension_table[EXT_ZVKSED] = true;
extension_table[EXT_ZVKSH] = true;
} else if (ext_str == "zvksc") {
extension_table[EXT_ZVBB] = true;
extension_table[EXT_ZVKB] = true;
extension_table[EXT_ZVBC] = true;
extension_table[EXT_ZVKSED] = true;
extension_table[EXT_ZVKSH] = true;
} else if (ext_str == "zvksg") {
extension_table[EXT_ZVBB] = true;
extension_table[EXT_ZVKB] = true;
extension_table[EXT_ZVKG] = true;
extension_table[EXT_ZVKSED] = true;
extension_table[EXT_ZVKSH] = true;
Expand Down
2 changes: 1 addition & 1 deletion riscv/insns/vandn_vv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

#include "zvk_ext_macros.h"

require_zvbb;
require_zvkb;

VI_VV_LOOP
({
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2 changes: 1 addition & 1 deletion riscv/insns/vandn_vx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

#include "zvk_ext_macros.h"

require_zvbb;
require_zvkb;

VI_VX_LOOP
({
Expand Down
2 changes: 1 addition & 1 deletion riscv/insns/vbrev8_v.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

#include "zvk_ext_macros.h"

require_zvbb;
require_zvkb;

VI_V_ULOOP
({
Expand Down
2 changes: 1 addition & 1 deletion riscv/insns/vrev8_v.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

#include "zvk_ext_macros.h"

require_zvbb;
require_zvkb;

VI_V_ULOOP
({
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2 changes: 1 addition & 1 deletion riscv/insns/vrol_vv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

#include "zvk_ext_macros.h"

require_zvbb;
require_zvkb;

// 'mask' selects the low log2(vsew) bits of the shift amount,
// to limit the maximum shift to "vsew - 1" bits.
Expand Down
2 changes: 1 addition & 1 deletion riscv/insns/vrol_vx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

#include "zvk_ext_macros.h"

require_zvbb;
require_zvkb;

// 'mask' selects the low log2(vsew) bits of the shift amount,
// to limit the maximum shift to "vsew - 1" bits.
Expand Down
2 changes: 1 addition & 1 deletion riscv/insns/vror_vi.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

#include "zvk_ext_macros.h"

require_zvbb;
require_zvkb;

// 'mask' selects the low log2(vsew) bits of the shift amount,
// to limit the maximum shift to "vsew - 1" bits.
Expand Down
2 changes: 1 addition & 1 deletion riscv/insns/vror_vv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

#include "zvk_ext_macros.h"

require_zvbb;
require_zvkb;

// 'mask' selects the low log2(vsew) bits of the shift amount,
// to limit the maximum shift to "vsew - 1" bits.
Expand Down
2 changes: 1 addition & 1 deletion riscv/insns/vror_vx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

#include "zvk_ext_macros.h"

require_zvbb;
require_zvkb;

// 'mask' selects the low log2(vsew) bits of the shift amount,
// to limit the maximum shift to "vsew - 1" bits.
Expand Down
1 change: 1 addition & 0 deletions riscv/isa_parser.h
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Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,7 @@ typedef enum {
EXT_ZVBC,
EXT_ZVFBFMIN,
EXT_ZVFBFWMA,
EXT_ZVKB,
EXT_ZVKG,
EXT_ZVKNED,
EXT_ZVKNHA,
Expand Down
13 changes: 8 additions & 5 deletions riscv/riscv.mk.in
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Original file line number Diff line number Diff line change
Expand Up @@ -1005,20 +1005,23 @@ riscv_insn_ext_zalasr = \
sw_rl \
sd_rl \

riscv_insn_ext_zvbb = \
riscv_insn_ext_zvkb = \
vandn_vv \
vandn_vx \
vbrev8_v \
vbrev_v \
vclz_v \
vcpop_v \
vctz_v \
vrev8_v \
vrol_vv \
vrol_vx \
vror_vi \
vror_vv \
vror_vx \

riscv_insn_ext_zvbb = \
$(riscv_insn_ext_zvkb) \
vbrev_v \
vclz_v \
vcpop_v \
vctz_v \
vwsll_vi \
vwsll_vv \
vwsll_vx \
Expand Down
10 changes: 9 additions & 1 deletion riscv/zvk_ext_macros.h
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@
// Predicate Macros
//

// Ensures that the ZVBB extension (vector crypto bitmanip) is present,
// Ensures that the ZVBB extension (vector basic bitmanip) is present,
// and the vector unit is enabled and in a valid state.
#define require_zvbb \
do { \
Expand All @@ -29,6 +29,14 @@
require_extension(EXT_ZVBC); \
} while (0)

// Ensures that the ZVKB extension (vector crypto bitmanip) is present,
// and the vector unit is enabled and in a valid state.
#define require_zvkb \
do { \
require_vector(true); \
require_extension(EXT_ZVKB); \
} while (0)

// Ensures that the ZVKG extension (vector Galois Field Multiplication)
// is present, and the vector unit is enabled and in a valid state.
#define require_zvkg \
Expand Down
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