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riscv-software-src / riscv-isa-sim Public

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vector: disassemble: Let operand ordering be vd, [vrf]s1, vs2 to vector multiply-add instructions #2505

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vector: disassemble: Let operand ordering be vd, [vrf]s1, vs2 to vector multiply-add instructions

vector: disassemble: Let operand ordering be vd, [vrf]s1, vs2 to vector multiply-add instructions #2505

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- Test Spike build (Ubuntu)
- Test Spike build (MacOS)
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Test Spike build (Ubuntu)

Test Spike build (Ubuntu)

succeeded Sep 2, 2024 in 7m 59s

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