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Fixed the overlapping operands to resolve the illegal instruction exception issue #501

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Fixed the overlapping operands to resolve the illegal instruction exception issue #501

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zeeshandildar
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Description

It resolves the illegal instruction exception as in one of the tests vsha2ms-e32.vv has overlapping registers which is not legal as mentioned in RISCV_ISA chapter (33.3.22)

Related Issues

#500

Ratified/Unratified Extensions

  • Ratified
  • Unratified

List Extensions

List the extensions that your PR affects. In case of unratified extensions, please provide a link to the spec draft that was referred to make this PR.

Reference Model Used

  • SAIL
  • Spike
  • Other - < SPECIFY HERE >

Mandatory Checklist:

  • All tests are compliant with the test-format spec present in this repo ?
  • Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
  • Ran the new tests on RISCOF in coverage mode
  • Link to Google-Drive folder containing the new coverage reports (See this for more info): < SPECIFY HERE >
  • Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
  • Changelog entry created with a minor patch

Optional Checklist:

  • RISCV-V CTG PR link if tests were generated using it : < SPECIFY HERE >
  • Were the tests hand-written/modified ?
  • Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
  • If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

cmuellner
cmuellner approved these changes Oct 9, 2024
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LGTM

@zeeshandildar
Merge remote-tracking branch 'upstream/dev' into dev
e40064c 
* upstream/dev:
  Run Multiple CI jobs in parallel (riscv-non-isa#522)
  Update requirements.txt to use >= required versions to allow for newer versions to be used (riscv-non-isa#519)
  Update Sail installation method (riscv-non-isa#521)
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@zeeshandildar @cmuellner @UmerShahidengr