Skip to content
View zeeshandildar's full-sized avatar
  • Semidynamics Technology Services
  • Barcelona, Spain
  • 01:32 (UTC +01:00)

Block or report zeeshandildar

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
zeeshandildar/README.md
  • 👋 Hi, I’m @zeeshandildar
  • 👀 I’m interested in RISCV based designs and their verification
  • 🌱 I’m currently working on verification of vector crypto extension
  • 💞️ I’m looking to collaborate on any project related to verification of RISCV based Core and Peripheral IPs
  • 📫 How to reach me [email protected]

Popular repositories Loading

  1. Practical-UVM-Step-By-Step Practical-UVM-Step-By-Step Public

    Forked from Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step

    This is the main repository for all the examples for the book Practical UVM

    Verilog

  2. vimrc vimrc Public

    Forked from amix/vimrc

    The ultimate Vim configuration (vimrc)

    Vim Script

  3. Simple_UVM Simple_UVM Public

    Forked from m-hariszafar/Simple_UVM

    Implements a simple UVM based testbench for a simple memory DUT.

    SystemVerilog

  4. uvm-testbench-tutorial-simple-adder uvm-testbench-tutorial-simple-adder Public

    Forked from m-hariszafar/uvm-testbench-tutorial-simple-adder

    A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology

    SystemVerilog

  5. Simple_alu_uvm_testbench Simple_alu_uvm_testbench Public

    SystemVerilog

  6. General General Public

    Shell