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Fixed ISA fields for Zca, CMO, and rv32e rotate tests #419

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Dec 27, 2023
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Fixed ISA fields for Zca, CMO, and rv32e rotate tests #419

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4 changes: 4 additions & 0 deletions CHANGELOG.md
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@@ -1,5 +1,9 @@
# CHANGELOG

## [3.8.6] -- 2013-12-24
- Fixed check ISA fields to include 32/64 in Zca and CMO tests. Note that the riscv-ctg CGFs have not been updated.
- Fixed check ISA fields in rv32e_m/B/src/ror-01 and rori-01 that listed I instead of E. Again, CGF has not been updated.

## [3.8.5] -- 2013-12-23
- Renamed rv32e_unratified to rv32e_m because the E extension has been ratified January 2023
- Copied missing ebreak.S and ecall.S tests from rv32i_m/privilege to rv32e_m/privilege and update ISA for E
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8 changes: 4 additions & 4 deletions riscv-test-suite/rv32e_m/B/src/ror-01.S
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Expand Up @@ -32,13 +32,13 @@ RVTEST_CODE_BEGIN

RVTEST_CASE(0,"//check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror)

RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zbkb.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror)

RVTEST_CASE(2,"//check ISA:=regex(.*I.*Zk.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror)
RVTEST_CASE(2,"//check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror)

RVTEST_CASE(3,"//check ISA:=regex(.*I.*Zkn.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror)
RVTEST_CASE(3,"//check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror)

RVTEST_CASE(4,"//check ISA:=regex(.*I.*Zks.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror)
RVTEST_CASE(4,"//check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ror)

RVTEST_SIGBASE(x2,signature_x2_1)

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6 changes: 3 additions & 3 deletions riscv-test-suite/rv32e_m/B/src/rori-01.S
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Expand Up @@ -34,11 +34,11 @@ RVTEST_CASE(0,"//check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True;def TEST_CASE

RVTEST_CASE(1,"//check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori)

RVTEST_CASE(2,"//check ISA:=regex(.*.*Zk.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori)
RVTEST_CASE(2,"//check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori)

RVTEST_CASE(3,"//check ISA:=regex(.*I.*Zkn.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori)
RVTEST_CASE(3,"//check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori)

RVTEST_CASE(4,"//check ISA:=regex(.*I.*Zks.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori)
RVTEST_CASE(4,"//check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rori)

RVTEST_SIGBASE(x5,signature_x5_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/C/src/clbu-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clbu)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clbu)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/C/src/clhu-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clhu)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clhu)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/C/src/cmul-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*Zca.*Zcb.*);def TEST_CASE_1=True;",cmul)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*M.*Zca.*Zcb.*);def TEST_CASE_1=True;",cmul)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/C/src/cnot-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",cnot)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",cnot)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/C/src/csb-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csb)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csb)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/C/src/csext.b-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.b)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.b)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/C/src/csext.h-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.h)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.h)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/C/src/csh-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csh)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csh)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/C/src/czext.b-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",czext.b)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",czext.b)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/C/src/czext.h-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",czext.h)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",czext.h)

RVTEST_SIGBASE(x1,signature_x1_1)

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6 changes: 3 additions & 3 deletions riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S
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Expand Up @@ -16,11 +16,11 @@
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the cbo.zero instruction of the RISC-V RV32ZicbozZicsr extension for the cbozero covergroup.
// This assembly file tests the cbo.zero instruction of the RISC-V RV32Zicboz extension for the cbozero covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IZicbozZicsr")
RVTEST_ISA("RV32IZicsr_Zicboz")

.section .text.init
.globl rvtest_entry_point
Expand All @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicboz.*Zicsr.*);def TEST_CASE_1=True;",cbozero)
RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zicsr.*Zicboz.*);def TEST_CASE_1=True;",cbozero)

RVTEST_SIGBASE(x2,signature_x2_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/clbu-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clbu)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clbu)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/clh-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clh)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clh)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/clhu-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clhu)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clhu)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/cmul-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*Zca.*Zcb.*);def TEST_CASE_1=True;",cmul)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*M.*Zca.*Zcb.*);def TEST_CASE_1=True;",cmul)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/cnot-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",cnot)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",cnot)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/csb-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csb)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csb)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/csext.b-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.b)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.b)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/csext.h-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.h)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",csext.h)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/csh-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csh)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",csh)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/czext.b-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",czext.b)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",czext.b)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/czext.h-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",czext.h)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*.Zbb.*);def TEST_CASE_1=True;",czext.h)

RVTEST_SIGBASE(x1,signature_x1_1)

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2 changes: 1 addition & 1 deletion riscv-test-suite/rv64i_m/C/src/czext.w-01.S
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Expand Up @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*.Zba.*);def TEST_CASE_1=True;",czext.w)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zca.*Zcb.*.Zba.*);def TEST_CASE_1=True;",czext.w)

RVTEST_SIGBASE(x1,signature_x1_1)

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6 changes: 3 additions & 3 deletions riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S
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Expand Up @@ -16,11 +16,11 @@
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the cbo.zero instruction of the RISC-V RV64ZicbozZicsr extension for the cbozero covergroup.
// This assembly file tests the cbo.zero instruction of the RISC-V RV64ZicsrZicboz extension for the cbozero covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IZicbozZicsr")
RVTEST_ISA("RV64IZicboz")

.section .text.init
.globl rvtest_entry_point
Expand All @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicboz.*Zicsr.*);def TEST_CASE_1=True;",cbozero)
RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zicsr.*Zicboz.*);def TEST_CASE_1=True;",cbozero)

RVTEST_SIGBASE(x3,signature_x3_1)

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