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src: Restore DMA tracing in Snitch DMA
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colluca committed Jul 12, 2024
1 parent 6a079ad commit b31dc28
Showing 1 changed file with 24 additions and 1 deletion.
25 changes: 24 additions & 1 deletion src/frontend/inst64/idma_inst64_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@

`include "common_cells/registers.svh"
`include "idma/typedef.svh"
`include "idma/tracer.svh"

/// Implements the tightly-coupled frontend. This module can directly be connected
/// to an accelerator bus in the snitch system
Expand All @@ -18,6 +19,7 @@ module idma_inst64_top #(
parameter int unsigned NumAxInFlight = 32'd3,
parameter int unsigned DMAReqFifoDepth = 32'd3,
parameter int unsigned NumChannels = 32'd1,
parameter int unsigned DMATracing = 32'd0,
parameter type axi_ar_chan_t = logic,
parameter type axi_aw_chan_t = logic,
parameter type axi_req_t = logic,
Expand Down Expand Up @@ -209,7 +211,6 @@ module idma_inst64_top #(
end



//--------------------------------------
// 2D Extension
//--------------------------------------
Expand Down Expand Up @@ -507,4 +508,26 @@ module idma_inst64_top #(
//--------------------------------------
`FF(idma_fe_req_q, idma_fe_req_d, '0)


//--------------------------------------
// DMA Tracer
//--------------------------------------
// only activate tracer if requested
if (DMATracing) begin

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[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L516

All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]"  location:{path:"src/frontend/inst64/idma_inst64_top.sv"  range:{start:{line:516  column:21}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
// derive the name of the trace file from the hart ID
string trace_file;
initial begin
// We need to schedule the assignment into a safe region, otherwise
// `hart_id_i` won't have a value assigned at the beginning of the first
// delta cycle.
/* verilator lint_off STMTDLY */
#0;
/* verilator lint_on STMTDLY */
$sformat(trace_file, "dma_trace_%05x.log", hart_id_i);
end
// attach the tracer
`IDMA_TRACER_RW_AXI(gen_backend[0].i_idma_backend_rw_axi, trace_file);
end


endmodule

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