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@sld-columbia System Level Design Group @ Columbia University

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    27 repositories

    • esp

      Public
      Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
      asicembedded-systemssystem-on-chipnetwork-on-chipacceleratorsfpgariscv
      C
      •
      Other
      •106•331•28•3•Updated Oct 1, 2024Oct 1, 2024

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •754•0•0•0•Updated Sep 4, 2024Sep 4, 2024

    • esp-accelerator-templates

      Public
      ESP Accelerator Templates
      C++
      •
      MIT License
      •7•5•0•1•Updated Sep 3, 2024Sep 3, 2024

    • esp-caches

      Public
      SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
      SystemVerilog
      •
      Apache License 2.0
      •6•17•0•0•Updated Sep 3, 2024Sep 3, 2024

    • ariane

      Public
      Ariane is a 6-stage RISC-V CPU capable of booting Linux
      SystemVerilog
      •
      Other
      •677•3•0•1•Updated Aug 2, 2024Aug 2, 2024

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •501•0•0•0•Updated Jul 23, 2024Jul 23, 2024

    • noc-tb

      Public
      VHDL
      •0•0•0•0•Updated Mar 14, 2024Mar 14, 2024

    • esp-docker

      Public
      Repository to create docker image for ESP
      Shell
      •3•4•1•0•Updated Feb 29, 2024Feb 29, 2024

    • linux

      Public
      C
      •
      Other
      •0•1•0•0•Updated Feb 29, 2024Feb 29, 2024

    • spikehard

      Public
      The open-source release of "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip"
      Verilog
      •
      MIT License
      •1•7•0•0•Updated Oct 7, 2023Oct 7, 2023

    • nvdla-sw

      Public
      NVDLA SW
      C++
      •
      Other
      •191•0•0•0•Updated Aug 20, 2023Aug 20, 2023

    • vortex

      Public
      Verilog
      •
      BSD 3-Clause "New" or "Revised" License
      •254•0•0•0•Updated Apr 13, 2023Apr 13, 2023

    • buildroot

      Public
      Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
      Makefile
      •
      Other
      •2.4k•0•0•0•Updated Oct 21, 2022Oct 21, 2022

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •140•0•0•0•Updated Sep 30, 2022Sep 30, 2022

    • riscv-dift

      Public
      SystemVerilog
      •
      Other
      •1•1•0•0•Updated Feb 7, 2022Feb 7, 2022

    • nvdla-hw

      Public
      RTL, Cmodel, and testbench for NVDLA
      Verilog
      •
      Other
      •567•3•0•0•Updated Sep 28, 2021Sep 28, 2021

    • axi_riscv_atomics

      Public
      AXI Adapter(s) for RISC-V Atomic Operations
      SystemVerilog
      •
      Other
      •15•2•0•0•Updated Sep 17, 2021Sep 17, 2021

    • axi

      Public
      AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
      SystemVerilog
      •
      Other
      •256•5•0•0•Updated Sep 17, 2021Sep 17, 2021

    • riscv-pk

      Public
      RISC-V Proxy Kernel
      C
      •
      Other
      •308•0•0•0•Updated Jun 2, 2021Jun 2, 2021

    • cryo-ai-models

      Public
      C++
      •0•0•0•0•Updated May 17, 2021May 17, 2021

    • zynq-template

      Public
      Template design and boot image for ZYNQ and ZYNQ Ultrascale+ Development Boards
      templatefpgazynq
      Makefile
      •
      MIT License
      •3•8•0•0•Updated Mar 26, 2021Mar 26, 2021

    • esp-chisel-accelerators

      Public
      Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
      Scala
      •
      Apache License 2.0
      •13•2•0•0•Updated Dec 14, 2020Dec 14, 2020

    • rv_plic

      Public
      Development Fork (unstable)
      SystemVerilog
      •
      Apache License 2.0
      •22•1•0•0•Updated Sep 30, 2020Sep 30, 2020

    • sld-lib-jenkins

      Public
      Shared library for Jenkins
      Groovy
      •0•0•0•0•Updated Jul 29, 2020Jul 29, 2020

    • hl5

      Public
      A 32-bit RISC-V Processor Designed with High-Level Synthesis
      C
      •
      Apache License 2.0
      •18•47•2•0•Updated Feb 6, 2020Feb 6, 2020

    • riscv-cores-list

      Public
      RISC-V Cores, SoC platforms and SoCs
      202•2•0•0•Updated Nov 19, 2019Nov 19, 2019

    • memgen

      Public
      Memory Generator for High Level Synthesis of ESP Accelerators
      Python
      •
      Apache License 2.0
      •0•0•0•0•Updated Nov 4, 2019Nov 4, 2019