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RISC-V Platform-Level Interrupt Controller

RV_PLIC module is to manage multiple interrupt events generated from the peripherals. It implements Platform-Level Interrupt Controller in RISC-V Privileges specification Section 7.

reg_rv_plic.py

The tool is to create register hjson file given values of number of sources, number of targets, and max value of priority. By default target is 1 and priority is 7 (8 level of priorities supported)

To change the value and to re-create hjson,

$ reg_rv_plic.py -s 64 -t 2 -p 15 rv_plic_reg.tpl.hjson > rv_plic_reg.hjson

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  • SystemVerilog 95.0%
  • Python 5.0%