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    293 repositories

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •265•1.1k•43•15•Updated Nov 11, 2024Nov 11, 2024

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •19•75•1•2•Updated Nov 11, 2024Nov 11, 2024

    • chimera

      Public
      Python
      •
      Other
      •1•9•9•1•Updated Nov 11, 2024Nov 11, 2024

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •45•275•4•7•Updated Nov 11, 2024Nov 11, 2024

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •28•90•7•8•Updated Nov 11, 2024Nov 11, 2024

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •2•21•0•0•Updated Nov 11, 2024Nov 11, 2024

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •15•26•4•3•Updated Nov 11, 2024Nov 11, 2024

    • Deeploy

      Public
      ONNX-to-C Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •6•14•1•3•Updated Nov 11, 2024Nov 11, 2024

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •132•371•65•10•Updated Nov 11, 2024Nov 11, 2024

    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP RISC-V Cores
      riscvdebug
      SystemVerilog
      •
      Other
      •72•224•28•5•Updated Nov 11, 2024Nov 11, 2024

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •688•16•1•8•Updated Nov 11, 2024Nov 11, 2024

    • memory_island

      Public
      An interleaved high-throughput low-contention L2 scratchpad memory.
      SystemVerilog
      •
      Other
      •1•1•4•3•Updated Nov 11, 2024Nov 11, 2024

    • redmule

      Public
      SystemVerilog
      •
      Other
      •12•35•1•3•Updated Nov 10, 2024Nov 10, 2024

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •47•195•7•24•Updated Nov 8, 2024Nov 8, 2024

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •11•16•7•1•Updated Nov 8, 2024Nov 8, 2024

    • ManyRVData

      Public
      0•0•0•0•Updated Nov 8, 2024Nov 8, 2024

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•8•0•2•Updated Nov 7, 2024Nov 7, 2024

    • pulp-detector

      Public
      C
      •2•12•1•0•Updated Nov 6, 2024Nov 6, 2024

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •52•51•13•6•Updated Nov 5, 2024Nov 5, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •145•513•30•8•Updated Nov 5, 2024Nov 5, 2024

    • cluster_icache

      Public
      An instruction cache for processor clusters, originally developed for the snitch cluster.
      SystemVerilog
      •
      Other
      •1•2•0•6•Updated Nov 5, 2024Nov 5, 2024

    • apb_gpio

      Public
      SystemVerilog
      •
      Other
      •18•8•0•0•Updated Nov 4, 2024Nov 4, 2024

    • ITA

      Public
      SystemVerilog
      •
      Other
      •3•9•0•1•Updated Nov 4, 2024Nov 4, 2024

    • fpu_ss

      Public
      CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor
      SystemVerilog
      •
      Other
      •8•9•1•0•Updated Nov 4, 2024Nov 4, 2024

    • regression_tests

      Public
      C
      •16•5•3•1•Updated Nov 4, 2024Nov 4, 2024

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •772•1•0•1•Updated Nov 3, 2024Nov 3, 2024

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •21•56•4•4•Updated Nov 1, 2024Nov 1, 2024

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •33•34•6•4•Updated Nov 1, 2024Nov 1, 2024

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •13•5•0•6•Updated Oct 31, 2024Oct 31, 2024

    • hwpe-datamover-example

      Public
      This is an example of an HCI-based HWPE used simply as a data mover.
      C
      •
      Other
      •3•0•0•1•Updated Oct 30, 2024Oct 30, 2024