Carfield is an open-research heterogeneous platform for safety, resilient and time-predictable systems. Originally conceived as automotive-oriented SoC, the high configurability of the platform makes it tunable to target a broader class of mixed-criticality applications' domains, such as automotive, space or industry.
Carfield is developed as part of the PULP project, a joint effort between ETH Zurich and the University of Bologna.
The rapid evolution of AI algorithms and the massive amount of sensed data across application-domains such as Automotive, Space and Cyber-Physical embedded systems (CPSs), call for a paradigm shift in the design of next generation of mixed-criticality systems (MCSs), from simple micro-controllers towards powerful and heterogeneous edge computers.
These must not only deliver outstanding performance and energy efficiency but also ensure steadfast safety, resilience, and security.
The Carfield platform aims to tackle these architectural challenges establishing itself as a pre-competitive heterogeneous platform for MCSs, underpinned by fully open-source Intellectual Properties (IPs).
Carfield showcases pioneering hardware solutions, addressing challenges related to time-predictable on/off-chip communication, robust fault recovery mechanisms, secure boot processes, cryptographic acceleration services, hardware-assisted virtualization, and accelerated computation for both floating-point and integer workloads.
- To learn how to build and use Carfield, see Getting Started.
- To learn about available simulation, FPGA, and ASIC targets, see Targets.
- For detailed information on Carfield's inner workings, consult the User Manual.
If you are impatient and have all needed dependencies, type:
make car-all
and then run a simulation with Questasim by typing:
make car-vsim-sim-build
make car-vsim-sim-run CHS_BINARY=./sw/tests/bare-metal/hostd/helloworld.car.l2.elfTo display the main Make build targets and their usage, from the root repository type:
make helpThe Make files are autodocumented.
It is possible to initialize an available technology design flow by running make tech-init after cloning the repo.
Unless specified otherwise in the respective file headers, all code checked into this repository is
made available under a permissive license. All hardware sources and tool scripts are licensed under
the Solderpad Hardware License 0.51 (see LICENSE) with the exception of generated register file
code (e.g. hw/regs/*.sv), which is generated by a fork of lowRISC's
regtool and licensed under
Apache 2.0. All software sources are licensed under Apache 2.0.