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MAM-WB Interface: Reduced to "Classic" Cycle only #27

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MAM-WB Interface: Reduced to "Classic" Cycle only #27

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8ae4cfd
Reduced MAM-WB interface functionality to WB Classic Cycles
Sep 5, 2016
3526fad
Simplified MAM-WB State Machine
Sep 5, 2016
d825352
Further reduced number of states
Sep 5, 2016
f8e305d
Removed reg type from cti_o and bte_o
Sep 5, 2016
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114 changes: 27 additions & 87 deletions modules/mam/wishbone/osd_mam_wb_if.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,8 @@ module osd_mam_wb_if
output reg [ADDR_WIDTH-1:0] addr_o,
output reg [DATA_WIDTH-1:0] dat_o,
input [DATA_WIDTH-1:0] dat_i,
output reg [2:0] cti_o,
output reg [1:0] bte_o,
output [2:0] cti_o,
output [1:0] bte_o,
output reg [SW-1:0] sel_o
);

Expand All @@ -53,13 +53,10 @@ module osd_mam_wb_if
(DATA_WIDTH == 16) ? 2 :
(DATA_WIDTH == 8) ? 1 : 'hx;

enum { STATE_IDLE, STATE_WRITE_LAST, STATE_WRITE_LAST_WAIT,
STATE_WRITE, STATE_WRITE_WAIT, STATE_READ,
STATE_READ_WAIT } state, nxt_state;
enum { STATE_IDLE, STATE_WRITE, STATE_WRITE_WAIT,
STATE_READ, STATE_READ_WAIT } state, nxt_state;

logic nxt_we_o;
logic [2:0] nxt_cti_o;
logic [1:0] nxt_bte_o;

reg [DATA_WIDTH-1:0] read_data_reg;
logic [DATA_WIDTH-1:0] nxt_read_data_reg;
Expand All @@ -81,22 +78,20 @@ module osd_mam_wb_if
end

we_o <= nxt_we_o;
cti_o <= nxt_cti_o;
bte_o <= nxt_bte_o;
read_data_reg <= nxt_read_data_reg;
dat_o_reg <= nxt_dat_o_reg;
addr_o <= nxt_addr_o;
beats <= nxt_beats;
end

assign cyc_o = stb_o;

assign cti_o = 3'b0;
assign bte_o = 2'b0;
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@wallento wallento Sep 5, 2016 •
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You will also need to remove the reg type from cti and bte too


//state & output logic
always_comb begin
nxt_state = state;
nxt_we_o = we_o;
nxt_cti_o = cti_o;
nxt_bte_o = 2'b0;
nxt_read_data_reg = read_data_reg;
nxt_dat_o_reg = dat_o_reg;
nxt_addr_o = addr_o;
Expand All @@ -118,64 +113,19 @@ module osd_mam_wb_if
nxt_addr_o = req_addr;
if (req_valid) begin
if (req_rw) begin
nxt_we_o = 1;
if (req_burst) begin
if (nxt_beats == 1) begin
nxt_cti_o = 3'b111;
if (write_valid) begin
nxt_state = STATE_WRITE_LAST;
nxt_dat_o_reg = write_data;
end else begin
nxt_state = STATE_WRITE_LAST_WAIT;
end
end else begin
nxt_cti_o = 3'b010;
nxt_bte_o = 2'b00;
if (write_valid) begin
nxt_state = STATE_WRITE;
nxt_dat_o_reg = write_data;
end else begin
nxt_state = STATE_WRITE_WAIT;
end
end
end else begin // !req_burst
nxt_cti_o = 3'b111;
if (write_valid) begin
nxt_state = STATE_WRITE_LAST;
nxt_dat_o_reg = write_data;
end else begin
nxt_state = STATE_WRITE_LAST_WAIT;
end
end // if (req_burst)
nxt_we_o = 1;
if (write_valid) begin
nxt_state = STATE_WRITE;
nxt_dat_o_reg = write_data;
end else begin
nxt_state = STATE_WRITE_WAIT;
end
end else begin // req_rw == 0
nxt_we_o = 0;
nxt_state = STATE_READ;
if (req_burst) begin
if (nxt_beats == 1) begin
nxt_cti_o = 3'b111;
end else begin
nxt_cti_o = 3'b010;
end
end else begin // !req_burst
nxt_cti_o = 3'b111;
end // if (req_burst)
end // if (req_rw)
end // if (req_valid)
end //STATE_IDLE
STATE_WRITE_LAST_WAIT: begin
write_ready = 1;
if (write_valid) begin
nxt_state = STATE_WRITE_LAST;
nxt_dat_o_reg = write_data;
end
end //STATE_WRITE_LAST_WAIT
STATE_WRITE_LAST: begin
stb_o = 1;
if (ack_i) begin
nxt_state = STATE_IDLE;
nxt_cti_o = 3'b000;
end
end //STATE_WRITE_LAST
STATE_WRITE_WAIT: begin
write_ready = 1;
if (write_valid) begin
Expand All @@ -187,25 +137,19 @@ module osd_mam_wb_if
STATE_WRITE: begin
stb_o = 1;
if (ack_i) begin
write_ready = 1;
nxt_addr_o = addr_o + DATA_WIDTH/8;
if (beats == 1) begin
nxt_cti_o=3'b111;
if (write_valid) begin
nxt_state = STATE_WRITE_LAST;
nxt_dat_o_reg = write_data;
end else begin
nxt_state = STATE_WRITE_LAST_WAIT;
end
end else begin // beats != 1
if (write_valid) begin
nxt_state = STATE_WRITE;
nxt_dat_o_reg = write_data;
nxt_beats = beats - 1;
end else begin
nxt_state = STATE_WRITE_WAIT;
end
end // if (beats == 1)
if (beats == 0) begin
nxt_state = STATE_IDLE;
end else begin // beats != 0
write_ready = 1;
nxt_addr_o = addr_o + DATA_WIDTH/8;
if (write_valid) begin
nxt_state = STATE_WRITE;
nxt_dat_o_reg = write_data;
nxt_beats = beats - 1;
end else begin
nxt_state = STATE_WRITE_WAIT;
end
end // if (beats == 0)
end // if (ack_i)
end // STATE_WRITE
STATE_READ: begin
Expand All @@ -220,10 +164,6 @@ module osd_mam_wb_if
STATE_READ_WAIT: begin
read_valid = 1;
if (read_ready) begin
if (beats == 1) begin
nxt_cti_o = 3'b111;
end

if (beats == 0) begin
nxt_state = STATE_IDLE;
end else begin
Expand Down