MAM-WB Interface: Reduced to "Classic" Cycle only #27
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added 3 commits
September 5, 2016 11:09
For that, CTI_O and BTE_O are set to be always zeros.
Reduced Write states.
Removed unneccessary write states.
| read_data_reg <= nxt_read_data_reg; | ||
| dat_o_reg <= nxt_dat_o_reg; | ||
| addr_o <= nxt_addr_o; | ||
| beats <= nxt_beats; | ||
| end | ||
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| assign cyc_o = stb_o; | ||
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| assign cti_o = 3'b0; | ||
| assign bte_o = 2'b0; |
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You will also need to remove the reg type from cti and bte too
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Done. Thanks. |
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@wallento is this still valid and should be merged? |
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In current implementation, no (useful) burst accesses are possible. Therefore "Classic" single read/writes suffice until redesign for issue #26 . Simplified code to reflect that.