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Add SoC config #681

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wants to merge 631 commits into from
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Add SoC config #681

wants to merge 631 commits into from

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infinitymdm
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@infinitymdm infinitymdm commented Mar 19, 2024

Changes in this PR apply only to the soc branch, not main or dev

This PR adds a new configuration file for the Wally RV64GC SoC using BSG's memory controller, as well as a number of changes relevant to our SoC tapeout effort.

Summary of changes:

  • Bring the soc branch (relatively) up-to-date with main
  • Integrate debug spec from Debug Support seed #823
  • Clean up previous SoC-related changes:
    • Delete testbench/testbench-soc.sv and merge its contents into `testbench/testbench.sv
    • Delete soc-specific dofiles
    • Use a few new config parameters to selectively enable PLL and BSG DMC support
    • Add a new config file config/soc/config.vh
  • Get BSG's memory controller talking to Wally over AHB
    • Rewrite ahbxuiconverter.sv with FSM-based control and waaay simpler datapath
    • Add memory-mapped registers for configuring the memory controller
    • Add memory-mapped registers for configuring TCI 28nm PLL IP
    • Add "First stage bootloader" assembly procedures (under soc/fsbl) that set up the aforementioned configuration registers with valid test parameters
  • Test Wally in SoC configuration
    • Configure testbench to use the Micron LPDDR model provided by BSG
    • Add self-checking procedure to tests/custom/lpddrtest
    • You can run tests against the SoC config using regression-wally --soc

@davidharrishmc
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I agree that I'd rather keep the ton of bsg stuff out of the wally-batch.do.

There's also a lot of unrelated files being committed here, such as copies of the crypto unit. Can you clean up the PR to only add the stuff you need?

@infinitymdm
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There's also a lot of unrelated files being committed here, such as copies of the crypto unit. Can you clean up the PR to only add the stuff you need?

Most of that is just to catch the soc branch up to main. If you prefer, I can open a separate PR to pull main into soc.

@davidharrishmc
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Ah, I understand. Disregard my comment.

@infinitymdm infinitymdm marked this pull request as ready for review March 28, 2024 03:01
@infinitymdm infinitymdm marked this pull request as draft May 30, 2024 21:17
rosethompson and others added 27 commits June 19, 2024 14:00
Removes *** from all system verilog
Partial fix for verilator +args. At least compiles.
Modified makefile riscv-dv to not simulation only generate tests.
Covergen doesn't produce stores and riscv-dv only generates tests
lint cleanup and divider optimization
@infinitymdm
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Closing for now pending #921. I'll open a new PR with just the memory controller changes rebased on top of main.

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6 participants