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Add SoC config #681
Add SoC config #681
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I agree that I'd rather keep the ton of bsg stuff out of the wally-batch.do. There's also a lot of unrelated files being committed here, such as copies of the crypto unit. Can you clean up the PR to only add the stuff you need? |
Most of that is just to catch the soc branch up to main. If you prefer, I can open a separate PR to pull main into soc. |
Ah, I understand. Disregard my comment. |
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Removes *** from all system verilog
Partial fix for verilator +args. At least compiles.
Modified makefile riscv-dv to not simulation only generate tests.
Covergen doesn't produce stores and riscv-dv only generates tests
…old if. PC=0 detection is disabled for now.
Update riscv-arch-test
lint cleanup and divider optimization
Closing for now pending #921. I'll open a new PR with just the memory controller changes rebased on top of main. |
Changes in this PR apply only to the soc branch, not main or dev
This PR adds a new configuration file for the Wally RV64GC SoC using BSG's memory controller, as well as a number of changes relevant to our SoC tapeout effort.
Summary of changes:
testbench/testbench-soc.sv
and merge its contents into `testbench/testbench.svconfig/soc/config.vh
soc/fsbl
) that set up the aforementioned configuration registers with valid test parameterstests/custom/lpddrtest
regression-wally --soc