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1. openhwgroup/cvw openhwgroup/cvw Public

   CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

   SystemVerilog 260 184

2. CharLib CharLib Public

   Open-source repository for a standard-cell library characterizer using complete open-source tools

   Python 19 2

3. SpringerBookArith04 SpringerBookArith04 Public

   These are files from my 2004 book, "Digital Computer Arithmetic Datapath Design Using Verilog HDL"

   Verilog 2

4. xchiplogo xchiplogo Public

   This is chiplogo a logo generator for VLSI chips.

   C 2 1

5. globalfoundries-pdk-libs-gf180mcu_osu_sc globalfoundries-pdk-libs-gf180mcu_osu_sc Public

   Forked from google/globalfoundries-pdk-libs-gf180mcu_osu_sc

   Digital standard cells for GF180MCU provided by Oklahoma State University.

   Tcl 3

6. Random Random Public

   Create C code to generate a bunch of random hex digits for use with SPICE decks

   C