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Spike Tandem Implementation using VCS simulator #1561
Spike Tandem Implementation using VCS simulator #1561
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❌ failed run, report available here. |
localparam bit ENABLE_WFI = 1'b0; | ||
// Spike zeros tval on all exception except memory faults | ||
// Spike still places 0 in TVAL for ENV_CALL_* exceptions. | ||
// This may eventually go away when Spike starts to handle TVAL for *all* exceptions. |
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Removed if comapre is done at Spike level
corev_apu/tb/common/SimDTM.sv
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@@ -65,17 +65,17 @@ module SimDTM( | |||
end | |||
else | |||
begin |
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to be cleaned-up
Mario, the Spike is not recompiled in GitHub Action, that maybe the reason why the CI does not pass. Maybe @zarubaf can help to fix the issue ? |
@zarubaf The Tandem PR is (quite) huge, can you also have a look to it ? |
@ASintzoff Can you have a look to the Tandem PR. Mario make a tval modification which need to be validated. We are waiting for your opinion on that. Moreover, as your have a solid reviewer reputation, we wonder whether you would could help in reviewing the PR |
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Awesome, thanks a lot for pushing this feature!
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Great result. Yesterday the Thales CI was broken. We will (try to) fix it Today. |
❌ failed run, report available here. |
If I can do something to help let me know 👍 |
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❌ failed run, report available here. |
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❌ failed run, report available here. |
@MarioOpenHWGroup I tried to make TVAL optional but it is used to generate RVFI. Removing it suppress the instruction trace generation and does not allow to do compare between Spike and RTL. Action is ongoing to generate RVFI wihtout the help of TVAL. |
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✔️ successful run, report available here. |
* Makefile (defines): Fix comment. (spike-tandem): Set default to empty (= disabled). (spike tandem verification): Change guarding condition. Adjust CFLAGS. Do not require definition of 'preload' (obsolete). (dpi): Change guarding condition. (CFLAGS): Use Spike headers from Spike installation dir. (src): Add mock_uart. (tbs): Add spike.sv when building in Spike tandem mode. Break long line. (questa-cmd): Use Spike library from Spike installation dir. (vcs): Move +permissive to the start of arg list. Add libriscv library when in Spike tandem mode. (dpi_build): New. * core/decoder.sv: Always enable WFI. * core/include/ariane_pkg.sv: Remove parameters ENABLE_CYCLE_COUNT and ENABLE_WFI. Fix and update * corev_apu/tb/ariane_tb.sv: Use RVFI to pass CVA6 state when in Spike tandem mode. Reformat UVM message. * corev_apu/tb/common/spike.sv: Use RFVI to pass CVA6 state. Guard parts of code with "`ifdef SPIKE_MISSING_DATA" when no suitable Spike data is available. Add progress messages. Use extended ANSI coloring for mismatch messages. * corev_apu/tb/ariane_tb.sv (spike): Add comment about parameterization of the CVA6 core. * Disabling JTAG and its DPI module as it has dependencies with ariane_dpi. Ariane DPI has to be refactored * Makefile: adding rvfi_pkg adding absolute paths to the incdir to avoid relative path issues move spike.sv from tbs to src * core/cva6.sv: change tval for new instr field of the scoreboard_entry_t change trap to support all kinds of exceptions and interrupts * core/decoder.sv: change tval for 0 and add the old tval value to instr field * core/include/ariane_pkg.sv: add instr field on scoreboard_entry_t * core/include/rvfi_pkg.sv: new file that has st_rvfi struct, compare function, spike init function * corev_apu/tb/common/spike.sv change module to support rvfi_pkg * verif/env/uvme/uvme_cva6_cfg.sv: rename scooreboarding_enable to scoreboard_enable rvfi_cfg.nret now properly set * verif/env/uvme/uvme_cva6_constants.sv: delete RVFI_NRET to avoid misconfigurations * verif/env/uvme/uvme_cva6_env.sv: rename scoreboarding unify rvfi_monitors into one * verif/env/uvme/uvme_cva6_pkg.sv: add cva6_config_pkg to be available in the components * verif/regress/install-spike.sh: change SPIKE_SRC_DIR to core-v-verif * verif/sim/Makefile: avoid reconfigure if a config.log exists add core_v_verif variable add spike-tandem variable add elfloader lib instead of ariane_dpi * verif/sim/cva6.py: solve trailing issues * verif/sim/cva6.yaml: delete steps variable #TODO add new timeout impl * verif/sim/cva6_spike_log_to_trace_csv.py: adapt for new spike impl * verif/tb/uvmt/cva6_tb_wrapper.sv: PRELOAD to elf_file * verif/tb/uvmt/uvmt_cva6_pkg.sv: add rvfi_pkg * verif/tb/uvmt/uvmt_cva6_tb.sv: add localparam RVFI_NRET add rvfi_cause * verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv: add factory override for spike * remove lib/dpi_dasm in favor of dpidasm of riscv-isa-sim * change ariane_tb to use new spike libfesvr dpi functions
Bumps [verif/core-v-verif](https://github.com/openhwgroup/core-v-verif) from `a687a60` to `6779193`. - [Release notes](https://github.com/openhwgroup/core-v-verif/releases) - [Commits](openhwgroup/core-v-verif@a687a60...6779193) --- updated-dependencies: - dependency-name: verif/core-v-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] <[email protected]>
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✔️ successful run, report available here. |
Huge work ! Thanks to you @MarioOpenHWGroup ! |
#1403 #1404 Implementation