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Update csr_access_test #37

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2 changes: 1 addition & 1 deletion regress/cv32e40x_full.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,7 @@ tests:

cv32e40x_csr_access_test:
description: CSR Access Mode Test
builds: [ uvmt_cv32e40x ]
builds: [ uvmt_cv32e40x_clic ]
dir: cv32e40x/sim/uvmt
cmd: make test TEST=cv32e40x_csr_access_test

Expand Down
7 changes: 6 additions & 1 deletion regress/cv32e40x_rel_check.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,11 @@ builds:
cmd: make comp_corev-dv comp
dir: cv32e40x/sim/uvmt

uvmt_cv32e40x_clic:
cmd: make comp_corev-dv comp
cfg: clic_default
dir: cv32e40x/sim/uvmt

uvmt_cv32e40x_pma_1:
cmd: make comp_corev-dv comp
cfg: pma_test_cfg_1
Expand Down Expand Up @@ -187,7 +192,7 @@ tests:
cmd: make test TEST=isa_fcov_holes

cv32e40x_csr_access_test:
build: uvmt_cv32e40x
build: uvmt_cv32e40x_clic
description: Randomly generated CSR access test
dir: cv32e40x/sim/uvmt
cmd: make test TEST=cv32e40x_csr_access_test
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11 changes: 5 additions & 6 deletions tests/programs/custom/cv32e40x_csr_access_test/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -3,22 +3,21 @@ CSR access test for (a practical subset of) implemented CSRs (i.e. not for the _
Generated from "riscv-dv"'s `scripts/gen_csr_test.py`, via core-v-verif's
`bin/gen_csr_access_test.py`, using the csr yaml definition in the core's repo.

Needs `CFG=clic_default`.

From top-level:
```
python3 ./bin/gen_csr_access_test.py \
./bin/gen_csr_access_test.py \
--core=cv32e40x \
--clint_enable \
--clic_enable \
--i_base_enable \
--m_ext_enable \
--umode_enable \
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--zc_enable \
--mhpmcounter_num 0 \
--mhpmcounter_num 1 \
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--num_triggers 0 \
--pmp_num_regions 0 \
--output=./cv32e40x/tests/programs/custom/cv32e40x_csr_access_test/ \
--m4
```
The above options were the most applicable at the time of writing and are subject to change.
Note that excluded options and parameters need targeted separate testing.

[comment]: # (TODO:silabs-robin Regen with "--xsecure_enable" etc after iss bugfix and rtl progression)
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