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Update pulp_riscv_dbg to pulp-platform/riscv-dbg@9155bfc #15436

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merged 2 commits into from
Oct 14, 2022

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andreaskurth
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@andreaskurth andreaskurth commented Oct 12, 2022

Update code from upstream repository https://github.com/pulp-platform/riscv-dbg to revision
9155bfc3006589d255cbfc4aa4df83e1567acbf3

This includes the fixes from upstream PRs pulp-platform/riscv-dbg#138, pulp-platform/riscv-dbg#139, and pulp-platform/riscv-dbg#140, which are relevant for M2.

The auto-generated overview of the changes is:

  • Update CHANGELOG.md (bluew)
  • tb: Ignore comb warnings (bluew)
  • dmi_jtag: Update dmi op field based on DMI response (Andreas Kurth)
  • dmi_jtag: Add mechanism for capturing failed DM op (Andreas Kurth)
  • dmi_jtag: Set busy error only if no sticky error is set (Andreas Kurth)
  • tb: Fix make vcsify (bluew)
  • tb: Rewrite buggy openocd test script in Python (bluew)
  • tb/Makefile: Use tabs (bluew)
  • tb: Fix testbench build (bluew)
  • dm_mem: Clear state of hart upon ndmreset (Andreas Kurth)
  • dmi_jtag_tap: Bring all state to initial value in Test-Logic-Reset (Andreas Kurth)
  • dmi_jtag: Take DMI response into account for reads (Andreas Kurth)
  • dm_csrs: Return busy DMI response if SBA is busy (Andreas Kurth)
  • dm_csrs: Return busy DMI response if command is busy (Andreas Kurth)
  • dm_csrs: Put entire dmi_resp_o through FIFO (Andreas Kurth)
  • dmi_jtag_tap: Use generic tech cells (Luca Colagrande)
  • jtag_test: Add read_dmi_exp_backoff() and sba_read_double() functions (Luca Colagrande)
  • Fix r/s/t/u-reset commands (epsilon)
  • Fix for 64-bit accesses (Arjan Bink)
  • Alternative fix for pull request 27 (Arjan Bink)

@andreaskurth andreaskurth requested a review from a team as a code owner October 12, 2022 12:27
@andreaskurth andreaskurth requested review from moidx, msfschaffner and tjaychen and removed request for a team October 12, 2022 12:27
@andreaskurth andreaskurth self-assigned this Oct 12, 2022
@andreaskurth andreaskurth added this to the Project: M2 milestone Oct 12, 2022
endtask
endclass

endpackage

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
File must end with a newline. [Style: posix-file-endings] [posix-eof]

/// They replace the functionality of `dmi_jtag_tap.sv`. The file is
/// pin-compatible so that by selecting the appropriate file for the target it
/// can be transparently managed without relying on tick defines.
module dmi_jtag_tap #(

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Declared module does not match the first dot-delimited component of file name: "dmi_bscane_tap" [Style: file-names] [module-filename]

// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51

interface JTAG_DV (

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Interface names must use lower_snake_case naming convention and end with _if. [Style: interface-conventions] [interface-name-style]


class jtag_driver #(
parameter int IrLength = 0,
parameter IDCODE = 'h1,

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Explicitly define a storage type for every parameter and localparam, (IDCODE). [Style: constants] [explicit-parameter-storage-type]

// abstracts the debug module
class riscv_dbg #(
parameter int IrLength = 5,
parameter IDCODE = 'h1,

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Explicitly define a storage type for every parameter and localparam, (IDCODE). [Style: constants] [explicit-parameter-storage-type]

assert(req.addr == req_mon.addr) else
$error("Invalid dmi request. Got address %0x instead of %0x.", req_mon.addr, req.addr);
assert(req.op == req_mon.op) else
$error("Invalid dmi request. Got op %0x instead of %0x.", req_mon.op, req.op);;

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Do not use consecutive null statements like ';;'. [Style: redundant-semicolons] [forbid-consecutive-null-statements]



// The DV interface additionally carries a clock signal.
interface DMI_BUS_DV #(

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Interface names must use lower_snake_case naming convention and end with _if. [Style: interface-conventions] [interface-name-style]

hw/vendor/pulp_riscv_dbg/src/dm_mem.sv Outdated Show resolved Hide resolved
hw/vendor/pulp_riscv_dbg/src/dm_mem.sv Outdated Show resolved Hide resolved
hw/vendor/pulp_riscv_dbg/src/dm_mem.sv Outdated Show resolved Hide resolved
@moidx moidx requested a review from sriyerg October 12, 2022 14:05
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LG for vendored C code. Will leave others to approve RTL. Thanks @andreaskurth!

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sriyerg commented Oct 12, 2022

Would you please run a full rv_dm regression locally to see if there are any fallouts?

./util/dvsim/dvsim.py hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson -i all --fixed-seed 1 

@andreaskurth
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Would you please run a full rv_dm regression locally to see if there are any fallouts?

./util/dvsim/dvsim.py hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson -i all --fixed-seed 1 

Sure 👍 All tests except the ones based on rv_dm_stress_all_vseq, which does not exist, pass:

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 0.550s 270.246us 1 1 100.00 %
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.480s 74.536us 1 1 100.00 %
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.460s 49.369us 1 1 100.00 %
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 0.830s 599.331us 1 1 100.00 %
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 0.480s 69.661us 1 1 100.00 %
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 0.600s 248.954us 1 1 100.00 %
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 0.590s 188.787us 1 1 100.00 %
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 4.150s 5.449ms 1 1 100.00 %
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.970s 2.250ms 1 1 100.00 %
V1 csr_hw_reset rv_dm_csr_hw_reset 0.810s 193.287us 1 1 100.00 %
V1 csr_rw rv_dm_csr_rw 0.780s 188.870us 1 1 100.00 %
V1 csr_bit_bash rv_dm_csr_bit_bash 16.660s 10.156ms 1 1 100.00 %
V1 csr_aliasing rv_dm_csr_aliasing 16.610s 6.968ms 1 1 100.00 %
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.060s 144.161us 1 1 100.00 %
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_rw 0.780s 188.870us 1 1 100.00 %
rv_dm_csr_aliasing 16.610s 6.968ms 1 1 100.00 %
V1 mem_walk rv_dm_mem_walk 0.340s 49.452us 1 1 100.00 %
V1 mem_partial_access rv_dm_mem_partial_access 0.330s 49.452us 1 1 100.00 %
V1 TOTAL 16 16 100.00 %
V2 idcode rv_dm_smoke 0.550s 270.246us 1 1 100.00 %
V2 sba rv_dm_sba_tl_access 1.640s 1.575ms 1 1 100.00 %
V2 bad_sba rv_dm_bad_sba_tl_access 1.220s 1.037ms 1 1 100.00 %
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.520s 1.384ms 1 1 100.00 %
V2 stress_all rv_dm_stress_all 0.400s 0 1 0.00 %
V2 alert_test rv_dm_alert_test 0.350s 51.535us 1 1 100.00 %
V2 tl_d_oob_addr_access rv_dm_tl_errors 2.010s 586.623us 1 1 100.00 %
V2 tl_d_illegal_access rv_dm_tl_errors 2.010s 586.623us 1 1 100.00 %
V2 tl_d_outstanding_access rv_dm_csr_hw_reset 0.810s 193.287us 1 1 100.00 %
rv_dm_csr_rw 0.780s 188.870us 1 1 100.00 %
rv_dm_csr_aliasing 16.610s 6.968ms 1 1 100.00 %
rv_dm_same_csr_outstanding 2.220s 849.542us 1 1 100.00 %
V2 tl_d_partial_access rv_dm_csr_hw_reset 0.810s 193.287us 1 1 100.00 %
rv_dm_csr_rw 0.780s 188.870us 1 1 100.00 %
rv_dm_csr_aliasing 16.610s 6.968ms 1 1 100.00 %
rv_dm_same_csr_outstanding 2.220s 849.542us 1 1 100.00 %
V2 TOTAL 6 7 85.71 %
V2S tl_intg_err rv_dm_sec_cm 0.640s 153.703us 1 1 100.00 %
rv_dm_tl_intg_err 5.220s 1.612ms 1 1 100.00 %
V2S TOTAL 2 2 100.00 %
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 0.440s 6.002us 0 1 0.00 %
V3 TOTAL 0 1 0.00 %
TOTAL 24 26 92.31 %

Failure Buckets

  • UVM_WARNING [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory. has 2 failures:
    • Test rv_dm_stress_all_with_rand_reset has 1 failures.

      • 0.rv_dm_stress_all_with_rand_reset.1
        Line 70, in log /home/dev/src/scratch/rv_dm-update/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

          UVM_WARNING @   6001752 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
          UVM_INFO @   6001752 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
          #### Factory Configuration (*)
        
          No instance overrides are registered with this factory
        
    • Test rv_dm_stress_all has 1 failures.

      • 0.rv_dm_stress_all.1
        Line 62, in log /home/dev/src/scratch/rv_dm-update/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log

          UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
          UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
          #### Factory Configuration (*)
        
          No instance overrides are registered with this factory
        

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sriyerg commented Oct 13, 2022

Would you please run a full rv_dm regression locally to see if there are any fallouts?

./util/dvsim/dvsim.py hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson -i all --fixed-seed 1 

Sure 👍 All tests except the ones based on rv_dm_stress_all_vseq, which does not exist, pass:

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 0.550s 270.246us 1 1 100.00 %
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.480s 74.536us 1 1 100.00 %
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.460s 49.369us 1 1 100.00 %
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 0.830s 599.331us 1 1 100.00 %
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 0.480s 69.661us 1 1 100.00 %
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 0.600s 248.954us 1 1 100.00 %
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 0.590s 188.787us 1 1 100.00 %
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 4.150s 5.449ms 1 1 100.00 %
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.970s 2.250ms 1 1 100.00 %
V1 csr_hw_reset rv_dm_csr_hw_reset 0.810s 193.287us 1 1 100.00 %
V1 csr_rw rv_dm_csr_rw 0.780s 188.870us 1 1 100.00 %
V1 csr_bit_bash rv_dm_csr_bit_bash 16.660s 10.156ms 1 1 100.00 %
V1 csr_aliasing rv_dm_csr_aliasing 16.610s 6.968ms 1 1 100.00 %
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.060s 144.161us 1 1 100.00 %
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_rw 0.780s 188.870us 1 1 100.00 %
rv_dm_csr_aliasing 16.610s 6.968ms 1 1 100.00 %
V1 mem_walk rv_dm_mem_walk 0.340s 49.452us 1 1 100.00 %
V1 mem_partial_access rv_dm_mem_partial_access 0.330s 49.452us 1 1 100.00 %
V1 TOTAL 16 16 100.00 %
V2 idcode rv_dm_smoke 0.550s 270.246us 1 1 100.00 %
V2 sba rv_dm_sba_tl_access 1.640s 1.575ms 1 1 100.00 %
V2 bad_sba rv_dm_bad_sba_tl_access 1.220s 1.037ms 1 1 100.00 %
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.520s 1.384ms 1 1 100.00 %
V2 stress_all rv_dm_stress_all 0.400s 0 1 0.00 %
V2 alert_test rv_dm_alert_test 0.350s 51.535us 1 1 100.00 %
V2 tl_d_oob_addr_access rv_dm_tl_errors 2.010s 586.623us 1 1 100.00 %
V2 tl_d_illegal_access rv_dm_tl_errors 2.010s 586.623us 1 1 100.00 %
V2 tl_d_outstanding_access rv_dm_csr_hw_reset 0.810s 193.287us 1 1 100.00 %
rv_dm_csr_rw 0.780s 188.870us 1 1 100.00 %
rv_dm_csr_aliasing 16.610s 6.968ms 1 1 100.00 %
rv_dm_same_csr_outstanding 2.220s 849.542us 1 1 100.00 %
V2 tl_d_partial_access rv_dm_csr_hw_reset 0.810s 193.287us 1 1 100.00 %
rv_dm_csr_rw 0.780s 188.870us 1 1 100.00 %
rv_dm_csr_aliasing 16.610s 6.968ms 1 1 100.00 %
rv_dm_same_csr_outstanding 2.220s 849.542us 1 1 100.00 %
V2 TOTAL 6 7 85.71 %
V2S tl_intg_err rv_dm_sec_cm 0.640s 153.703us 1 1 100.00 %
rv_dm_tl_intg_err 5.220s 1.612ms 1 1 100.00 %
V2S TOTAL 2 2 100.00 %
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 0.440s 6.002us 0 1 0.00 %
V3 TOTAL 0 1 0.00 %
TOTAL 24 26 92.31 %

Failure Buckets

  • UVM_WARNING [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory. has 2 failures:

    • Test rv_dm_stress_all_with_rand_reset has 1 failures.

      • 0.rv_dm_stress_all_with_rand_reset.1
        Line 70, in log /home/dev/src/scratch/rv_dm-update/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
          UVM_WARNING @   6001752 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
          UVM_INFO @   6001752 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
          #### Factory Configuration (*)
        
          No instance overrides are registered with this factory
        
    • Test rv_dm_stress_all has 1 failures.

      • 0.rv_dm_stress_all.1
        Line 62, in log /home/dev/src/scratch/rv_dm-update/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
          UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
          UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
          #### Factory Configuration (*)
        
          No instance overrides are registered with this factory
        

Awesome, thanks!

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LGTM, thanks! Will recommend 1+ designer approval before merging.

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andreaskurth commented Oct 13, 2022

I'm struggling to waive the lint error

LOOP_VAR_OP: dm_mem.sv:274 Loop variable 'dc' is in arithmetic expression 'dc < (dm::DataCount - 1)' with non-constant terms

I added this:

waive -rules LOOP_VAR_OP -location {dm_mem.sv} \
-regexp {Loop variable 'dc' is in arithmetic expression 'dc < (dm::DataCount - 1)' with non-constant terms} \
-comment "This is incorrect because all terms except the loop variable are constant in the arithmetic expression."

but the tool still flags an error. We don't have access to that linter, and I don't want to flood CI with trial & error. Any inputs would be highly appreciated

@vogelpi
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vogelpi commented Oct 13, 2022

I'm struggling to waive the lint error

LOOP_VAR_OP: dm_mem.sv:274 Loop variable 'dc' is in arithmetic expression 'dc < (dm::DataCount - 1)' with non-constant terms

I added this:

waive -rules LOOP_VAR_OP -location {dm_mem.sv} \
-regexp {Loop variable 'dc' is in arithmetic expression 'dc < (dm::DataCount - 1)' with non-constant terms} \
-comment "This is incorrect because all terms except the loop variable are constant in the arithmetic expression."

but the tool still flags an error. We don't have access to that linter, and I don't want to flood CI with trial & error. Any inputs would be highly appreciated

I remember a similar issue in the past. I think you need to change -regexp to -msg - IIRC -regexp has some issues with the ticks in this case. It's usually good to grep parts of the warning message to see how the waiver can be formulated. In this case, grepping for arithmetic expression gives an example in hw/ip/prim/lint/prim_lfsr.waiver:

waive -rules {LOOP_VAR_OP} -location {prim_lfsr.sv} -msg {Loop variable 'k' is in arithmetic expression '(k + shift) % gen_out_non_linear.NumSboxes' with non-constant terms} \
      -comment "This message is a false positive in this context, since the function inputs are constant."

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LGTM with just some minor comments on the patches. I haven't done an in-depth review of the vendored-in RTL changes though. But we have done most of the upstream changes ourselves anyway.

@@ -0,0 +1,2 @@
.bender/
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Do we usually exclude such files from the vendoring? I guess not.

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We can instruct the vendor tool to exclude these files by enumerating the exclusion paths in the *.vendor.hjson:

exclude_from_upstream: [
"src/dm_obi_top.sv",
"src_files.yml",
# We always exclude .clang-format from upstream repos
"tb/.clang-format",
]

@@ -0,0 +1,45 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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There is already a lint fix patch. I think the new fixes of this patch could have been merged into the other patch. But in the interest of time, I think this is okay.

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Hm since we actually have a patch repository we should move the patches there if possible.
This will make it easier to modify&replay these patches in the future.

Sorry I don't want to unnecessarily draw this out - let me know if I can help with this.

@@ -37,20 +37,20 @@ index 350c6c5..38d7b51 100644
- logic resp_queue_empty;
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Did you directly edit this file instead of regenerating the patch? In the interest of time, I think this is okay.

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I think it would still be good to use the patching repository for this so that this can easily be generated automatically. It looks like this is already set up in the vendor file:

patch_repo: {
url: "[email protected]:lowRISC/riscv-dbg.git",
rev_base: "master",
rev_patched: "ot",
},

So it would just be a matter of moving the patch to the ot branch here and invoking the vendor tool with the --refresh-patches switch:

$ util/vendor.py --refresh-patches --update --commit

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I tried that but it failed. I think our patch repository does not include patches from at least the last two PRs updating hw/vendor/pulp_riscv_dbg: #12613, #12728. In the interest of time, I did not spend the effort to first update the patch repository and port the patches there. But if you think that should be done now, I'll do it.

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I understand. Your approach is reasonable. Let's move forward and leave the cleanup for another time.

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I created #15506 to track this

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Ok, SGTM!

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msfschaffner commented Oct 13, 2022

I'm struggling to waive the lint error

LOOP_VAR_OP: dm_mem.sv:274 Loop variable 'dc' is in arithmetic expression 'dc < (dm::DataCount - 1)' with non-constant terms

I added this:

waive -rules LOOP_VAR_OP -location {dm_mem.sv} \
-regexp {Loop variable 'dc' is in arithmetic expression 'dc < (dm::DataCount - 1)' with non-constant terms} \
-comment "This is incorrect because all terms except the loop variable are constant in the arithmetic expression."

but the tool still flags an error. We don't have access to that linter, and I don't want to flood CI with trial & error. Any inputs would be highly appreciated

I remember a similar issue in the past. I think you need to change -regexp to -msg - IIRC -regexp has some issues with the ticks in this case. It's usually good to grep parts of the warning message to see how the waiver can be formulated. In this case, grepping for arithmetic expression gives an example in hw/ip/prim/lint/prim_lfsr.waiver:

waive -rules {LOOP_VAR_OP} -location {prim_lfsr.sv} -msg {Loop variable 'k' is in arithmetic expression '(k + shift) % gen_out_non_linear.NumSboxes' with non-constant terms} \
      -comment "This message is a false positive in this context, since the function inputs are constant."

I think you need to escape brackets when using -regexp since they are otherwise interpreted. If no regex'ing is needed here, switching to -msg as @vogelpi suggested should do the trick.

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I'm struggling to waive the lint error

LOOP_VAR_OP: dm_mem.sv:274 Loop variable 'dc' is in arithmetic expression 'dc < (dm::DataCount - 1)' with non-constant terms

I added this:

waive -rules LOOP_VAR_OP -location {dm_mem.sv} \
-regexp {Loop variable 'dc' is in arithmetic expression 'dc < (dm::DataCount - 1)' with non-constant terms} \
-comment "This is incorrect because all terms except the loop variable are constant in the arithmetic expression."

but the tool still flags an error. We don't have access to that linter, and I don't want to flood CI with trial & error. Any inputs would be highly appreciated

I remember a similar issue in the past. I think you need to change -regexp to -msg - IIRC -regexp has some issues with the ticks in this case. It's usually good to grep parts of the warning message to see how the waiver can be formulated. In this case, grepping for arithmetic expression gives an example in hw/ip/prim/lint/prim_lfsr.waiver:

waive -rules {LOOP_VAR_OP} -location {prim_lfsr.sv} -msg {Loop variable 'k' is in arithmetic expression '(k + shift) % gen_out_non_linear.NumSboxes' with non-constant terms} \
      -comment "This message is a false positive in this context, since the function inputs are constant."

That did the trick, thanks for your help!

Update code from upstream repository https://github.com/pulp-
platform/riscv-dbg to revision
9155bfc3006589d255cbfc4aa4df83e1567acbf3

* Update CHANGELOG.md (bluew)
* tb: Ignore comb warnings (bluew)
* dmi_jtag: Update `dmi` `op` field based on DMI response (Andreas
  Kurth)
* dmi_jtag: Add mechanism for capturing failed DM op (Andreas Kurth)
* dmi_jtag: Set busy error only if no sticky error is set (Andreas
  Kurth)
* tb: Fix make vcsify (bluew)
* tb: Rewrite buggy openocd test script in Python (bluew)
* tb/Makefile: Use tabs (bluew)
* tb: Fix testbench build (bluew)
* dm_mem: Clear state of hart upon ndmreset (Andreas Kurth)
* dmi_jtag_tap: Bring all state to initial value in Test-Logic-Reset
  (Andreas Kurth)
* dmi_jtag: Take DMI response into account for reads (Andreas Kurth)
* dm_csrs: Return busy DMI response if SBA is busy (Andreas Kurth)
* dm_csrs: Return busy DMI response if command is busy (Andreas Kurth)
* dm_csrs: Put entire `dmi_resp_o` through FIFO (Andreas Kurth)
* dmi_jtag_tap: Use generic tech cells (Luca Colagrande)
* jtag_test: Add `read_dmi_exp_backoff()` and `sba_read_double()`
  functions (Luca Colagrande)
* Fix r/s/t/u-reset commands (epsilon)
* Fix for 64-bit accesses (Arjan Bink)
* Alternative fix for pull request 27 (Arjan Bink)

Signed-off-by: Andreas Kurth <[email protected]>
Signed-off-by: Andreas Kurth <[email protected]>
@andreaskurth
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Rebased on master and force-pushed to retrigger CI (which was failing on FPGA tests due to transient CI problems).

@msfschaffner msfschaffner merged commit 4f8e48e into lowRISC:master Oct 14, 2022
@andreaskurth andreaskurth deleted the rv_dm-update branch October 24, 2022 12:55
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5 participants