[rv_dm] Fix lint

Signed-off-by: Andreas Kurth <[email protected]>

hw/ip/rv_dm/lint/rv_dm.waiver

@@ -81,6 +81,9 @@ waive -rules ONE_BRANCH    -location {dm_mem.sv} -regexp {unique case statement
       -comment "easier to write this way for extendability"
 waive -rules NOT_READ -location {dm_mem.sv} -regexp {Signal 'ac_ar.(regno.13.|zero1)' is not read from in module 'dm_mem'} \
       -comment "These bits and fields are not used, but all other bits and fields are used"
+waive -rules LOOP_VAR_OP -location {dm_mem.sv} \
+      -msg {Loop variable 'dc' is in arithmetic expression 'dc < (dm::DataCount - 1)' with non-constant terms} \
+      -comment "This is incorrect because all terms except the loop variable are constant in the arithmetic expression."
 
 # dm_sba
 waive -rules HIER_BRANCH_NOT_READ  -location {dm_sba.sv}            -regexp {Net 'dmactive_i' is not read from in module 'dm_sba'} \

hw/vendor/patches/pulp_riscv_dbg/0003-Fix-lint.patch

@@ -0,0 +1,45 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andreas Kurth <[email protected]>
+Date: Wed, 12 Oct 2022 12:52:14 +0000
+Subject: [PATCH] Fix lint
+
+Signed-off-by: Andreas Kurth <[email protected]>
+---
+ src/dm_mem.sv |  14 +++++++++-------
+ 1 file changed, 9 insertions(+), 5 deletions(-)
+
+diff --git a/src/dm_mem.sv b/src/dm_mem.sv
+index c1cc0e87b..cb95e2fc0 100644
+--- a/src/dm_mem.sv
++++ b/src/dm_mem.sv
+@@ -265,12 +265,13 @@ module dm_mem #(
+           // core can write data registers
+           [DataBaseAddr:DataEndAddr]: begin
+             data_valid_o = 1'b1;
+-            for (int dc = 0; dc < dm::DataCount; dc++) begin
++            for (int unsigned dc = 0; dc < dm::DataCount; dc++) begin
+               if ((addr_i[DbgAddressBits-1:2] - DataBaseAddr[DbgAddressBits-1:2]) == dc) begin
+-                for (int i = 0; i < $bits(be_i); i++) begin
++                for (int unsigned i = 0; i < $bits(be_i); i++) begin
+                   if (be_i[i]) begin
+                     if (i>3) begin // for upper 32bit data write (only used for BusWidth ==  64)
+-                      if ((dc+1) < dm::DataCount) begin // ensure we write to an implemented data register
++                      // ensure we write to an implemented data register
++                      if (dc < (dm::DataCount - 1)) begin
+                         data_bits[dc+1][(i-4)*8+:8] = wdata_i[i*8+:8];
+                       end
+                     end else begin // for lower 32bit data write
+@@ -310,8 +311,11 @@ module dm_mem #(
+
+           [DataBaseAddr:DataEndAddr]: begin
+             rdata_d = {
+-                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3] - DataBaseAddr[DbgAddressBits-1:3]) << 1) + 1'b1)],
+-                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3] - DataBaseAddr[DbgAddressBits-1:3]) << 1))]
++                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3]
++                                                      - DataBaseAddr[DbgAddressBits-1:3]) << 1)
++                                                    + 1'b1)],
++                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3]
++                                                      - DataBaseAddr[DbgAddressBits-1:3]) << 1))]
+                       };
+           end
+

hw/vendor/pulp_riscv_dbg/src/dm_mem.sv

@@ -265,12 +265,13 @@ module dm_mem #(
           // core can write data registers
           [DataBaseAddr:DataEndAddr]: begin
             data_valid_o = 1'b1;
-            for (int dc = 0; dc < dm::DataCount; dc++) begin
+            for (int unsigned dc = 0; dc < dm::DataCount; dc++) begin
               if ((addr_i[DbgAddressBits-1:2] - DataBaseAddr[DbgAddressBits-1:2]) == dc) begin
-                for (int i = 0; i < $bits(be_i); i++) begin
+                for (int unsigned i = 0; i < $bits(be_i); i++) begin
                   if (be_i[i]) begin
                     if (i>3) begin // for upper 32bit data write (only used for BusWidth ==  64)
-                      if ((dc+1) < dm::DataCount) begin // ensure we write to an implemented data register
+                      // ensure we write to an implemented data register
+                      if (dc < (dm::DataCount - 1)) begin
                         data_bits[dc+1][(i-4)*8+:8] = wdata_i[i*8+:8];
                       end
                     end else begin // for lower 32bit data write
@@ -310,8 +311,11 @@ module dm_mem #(
 
           [DataBaseAddr:DataEndAddr]: begin
             rdata_d = {
-                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3] - DataBaseAddr[DbgAddressBits-1:3]) << 1) + 1'b1)],
-                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3] - DataBaseAddr[DbgAddressBits-1:3]) << 1))]
+                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3]
+                                                      - DataBaseAddr[DbgAddressBits-1:3]) << 1)
+                                                    + 1'b1)],
+                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3]
+                                                      - DataBaseAddr[DbgAddressBits-1:3]) << 1))]
                       };
           end