Update pulp_riscv_dbg to pulp-platform/riscv-dbg@9155bfc

Update code from upstream repository https://github.com/pulp- platform/riscv-dbg to revision 9155bfc3006589d255cbfc4aa4df83e1567acbf3 * Update CHANGELOG.md (bluew) * tb: Ignore comb warnings (bluew) * dmi_jtag: Update `dmi` `op` field based on DMI response (Andreas Kurth) * dmi_jtag: Add mechanism for capturing failed DM op (Andreas Kurth) * dmi_jtag: Set busy error only if no sticky error is set (Andreas Kurth) * tb: Fix make vcsify (bluew) * tb: Rewrite buggy openocd test script in Python (bluew) * tb/Makefile: Use tabs (bluew) * tb: Fix testbench build (bluew) * dm_mem: Clear state of hart upon ndmreset (Andreas Kurth) * dmi_jtag_tap: Bring all state to initial value in Test-Logic-Reset (Andreas Kurth) * dmi_jtag: Take DMI response into account for reads (Andreas Kurth) * dm_csrs: Return busy DMI response if SBA is busy (Andreas Kurth) * dm_csrs: Return busy DMI response if command is busy (Andreas Kurth) * dm_csrs: Put entire `dmi_resp_o` through FIFO (Andreas Kurth) * dmi_jtag_tap: Use generic tech cells (Luca Colagrande) * jtag_test: Add `read_dmi_exp_backoff()` and `sba_read_double()` functions (Luca Colagrande) * Fix r/s/t/u-reset commands (epsilon) * Fix for 64-bit accesses (Arjan Bink) * Alternative fix for pull request 27 (Arjan Bink) Signed-off-by: Andreas Kurth <[email protected]>
lowRISC · Oct 14, 2022 · 8fad3b3 · 8fad3b3
1 parent 5e4f0a3
commit 8fad3b3
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diff --git a/hw/vendor/patches/pulp_riscv_dbg/0001-Use-lowrisc-instead-of-PULP-primitives.patch b/hw/vendor/patches/pulp_riscv_dbg/0001-Use-lowrisc-instead-of-PULP-primitives.patch
@@ -37,20 +37,20 @@ index 350c6c5..38d7b51 100644
 -  logic        resp_queue_empty;
 -  logic        resp_queue_push;
 -  logic        resp_queue_pop;
-   logic [31:0] resp_queue_data;
 
    localparam dm::dm_csr_e DataEnd = dm::dm_csr_e'(dm::Data0 + {4'h0, dm::DataCount} - 8'h1);
+   localparam dm::dm_csr_e ProgBufEnd = dm::dm_csr_e'(dm::ProgBuf0 + {4'h0, dm::ProgBufSize} - 8'h1);
 @@ -181,9 +178,6 @@ module dm_csrs #(
- 
-   // a successful response returns zero
-   assign dmi_resp_o.resp = dm::DTM_SUCCESS;
+
+   dm::dmi_resp_t resp_queue_inp;
+
 -  assign dmi_resp_valid_o     = ~resp_queue_empty;
 -  assign dmi_req_ready_o      = ~resp_queue_full;
 -  assign resp_queue_push      = dmi_req_valid_i & dmi_req_ready_o;
    // SBA
    assign sbautoincrement_o = sbcs_q.sbautoincrement;
    assign sbreadonaddr_o    = sbcs_q.sbreadonaddr;
-@@ -551,28 +545,29 @@ module dm_csrs #(
+@@ -579,28 +573,29 @@ module dm_csrs #(
    assign progbuf_o   = progbuf_q;
    assign data_o      = data_q;
 
@@ -63,10 +63,10 @@ index 350c6c5..38d7b51 100644
 +
    // response FIFO
 -  fifo_v2 #(
--    .dtype            ( logic [31:0]         ),
--    .DEPTH            ( 2                    )
+-    .dtype            ( logic [$bits(dmi_resp_o)-1:0] ),
+-    .DEPTH            ( 2                             )
 +  prim_fifo_sync #(
-+    .Width   (32),
++    .Width   ($bits(dmi_resp_o)),
 +    .Pass    (1'b0),
 +    .Depth   (2)
    ) i_fifo (
@@ -79,17 +79,17 @@ index 350c6c5..38d7b51 100644
 -    .empty_o          ( resp_queue_empty     ),
 -    .alm_full_o       (                      ),
 -    .alm_empty_o      (                      ),
--    .data_i           ( resp_queue_data      ),
+-    .data_i           ( resp_queue_inp       ),
 -    .push_i           ( resp_queue_push      ),
--    .data_o           ( dmi_resp_o.data      ),
+-    .data_o           ( dmi_resp_o           ),
 -    .pop_i            ( resp_queue_pop       )
 +    .clk_i   ( clk_i                ),
 +    .rst_ni  ( dmi_rst_ni           ), // reset only when system is re-set
 +    .clr_i   ( 1'b0                 ),
-+    .wdata_i ( resp_queue_data      ),
++    .wdata_i ( resp_queue_inp       ),
 +    .wvalid_i( dmi_req_valid_i      ),
 +    .wready_o( dmi_req_ready_o      ),
-+    .rdata_o ( dmi_resp_o.data      ),
++    .rdata_o ( dmi_resp_o           ),
 +    .rvalid_o( dmi_resp_valid_o     ),
 +    .rready_i( dmi_resp_ready_i     ),
 +    .full_o  (                      ), // Unused
@@ -287,12 +287,12 @@ index 0c188c0..a804da0 100644
    // ----------------
 -  logic tck_n, tck_ni;
 -
--  cluster_clock_inverter i_tck_inv (
+-  tc_clk_inverter i_tck_inv (
 -    .clk_i ( tck_i  ),
 -    .clk_o ( tck_ni )
 -  );
 -
--  pulp_clock_mux2 i_dft_tck_mux (
+-  tc_clk_mux2 i_dft_tck_mux (
 -    .clk0_i    ( tck_ni     ),
 -    .clk1_i    ( tck_i      ), // bypass the inverted clock for testing
 -    .clk_sel_i ( testmode_i ),

diff --git a/hw/vendor/pulp_riscv_dbg.lock.hjson b/hw/vendor/pulp_riscv_dbg.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/pulp-platform/riscv-dbg
-    rev: 69be5ddc03ea1688c0eab47d6ed9d0e8725beda1
+    rev: 9155bfc3006589d255cbfc4aa4df83e1567acbf3
   }
 }
diff --git a/hw/vendor/pulp_riscv_dbg/.gitignore b/hw/vendor/pulp_riscv_dbg/.gitignore
@@ -0,0 +1,2 @@
+.bender/
+Bender.lock
diff --git a/hw/vendor/pulp_riscv_dbg/CHANGELOG.md b/hw/vendor/pulp_riscv_dbg/CHANGELOG.md
@@ -5,6 +5,18 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
 
 ## [Unreleased]
+## [0.6.0] - 2022-10-11
+### Fixed
+- Testbench build (#141, #142)
+- remote_bitbang tb build for newer GCC versions (#133) [@epsilon537](https://github.com/noytzach)
+- 32-bit access to abstract data (#27) [@Silabs-ArjanB](https://github.com/Silabs-ArjanB)
+- `dm_mem`: Clear state of hart upon ndmreset (#140) [@andreaskurth](https://github.com/andreaskurth)
+- `dmi_jtag_tap`: Bring all state to initial value in test-logic-reset (#139) [@andreaskurth](https://github.com/andreaskurth)
+- Fix DMI response when command or SBA are busy (#138) [@andreaskurth](https://github.com/andreaskurth)
+
+### Changed
+- Add expontential backoff to read_dmi in tb (#134) [@colluca](https://github.com/colluca)
+
 ## [0.5.1] - 2022-04-12
 ### Fixed
 - Fixed dmi_bscane_tap top-level signals

diff --git a/hw/vendor/pulp_riscv_dbg/ci/veri-run-openocd-compliance.sh b/hw/vendor/pulp_riscv_dbg/ci/veri-run-openocd-compliance.sh
diff --git a/hw/vendor/pulp_riscv_dbg/src/dm_csrs.sv b/hw/vendor/pulp_riscv_dbg/src/dm_csrs.sv
@@ -87,7 +87,6 @@ module dm_csrs #(
   dm::dtm_op_e dtm_op;
   assign dtm_op = dm::dtm_op_e'(dmi_req_i.op);
 
-  logic [31:0] resp_queue_data;
 
   localparam dm::dm_csr_e DataEnd = dm::dm_csr_e'(dm::Data0 + {4'h0, dm::DataCount} - 8'h1);
   localparam dm::dm_csr_e ProgBufEnd = dm::dm_csr_e'(dm::ProgBuf0 + {4'h0, dm::ProgBufSize} - 8'h1);
@@ -176,8 +175,8 @@ module dm_csrs #(
 
   logic [HartSelLen-1:0] selected_hart;
 
-  // a successful response returns zero
-  assign dmi_resp_o.resp = dm::DTM_SUCCESS;
+  dm::dmi_resp_t resp_queue_inp;
+
   // SBA
   assign sbautoincrement_o = sbcs_q.sbautoincrement;
   assign sbreadonaddr_o    = sbcs_q.sbreadonaddr;
@@ -273,7 +272,8 @@ module dm_csrs #(
     sbaddr_d            = 64'(sbaddress_i);
     sbdata_d            = sbdata_q;
 
-    resp_queue_data         = 32'h0;
+    resp_queue_inp.data     = 32'h0;
+    resp_queue_inp.resp     = dm::DTM_SUCCESS;
     cmd_valid_d             = 1'b0;
     sbaddress_write_valid_o = 1'b0;
     sbdata_read_valid_o     = 1'b0;
@@ -288,62 +288,70 @@ module dm_csrs #(
     if (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) begin
       unique case (dm_csr_addr) inside
         [(dm::Data0):DataEnd]: begin
-          resp_queue_data = data_q[$clog2(dm::DataCount)'(autoexecdata_idx)];
+          resp_queue_inp.data = data_q[$clog2(dm::DataCount)'(autoexecdata_idx)];
           if (!cmdbusy_i) begin
             // check whether we need to re-execute the command (just give a cmd_valid)
             cmd_valid_d = abstractauto_q.autoexecdata[autoexecdata_idx];
           // An abstract command was executing while one of the data registers was read
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
-        dm::DMControl:    resp_queue_data = dmcontrol_q;
-        dm::DMStatus:     resp_queue_data = dmstatus;
-        dm::Hartinfo:     resp_queue_data = hartinfo_aligned[selected_hart];
-        dm::AbstractCS:   resp_queue_data = abstractcs;
-        dm::AbstractAuto: resp_queue_data = abstractauto_q;
+        dm::DMControl:    resp_queue_inp.data = dmcontrol_q;
+        dm::DMStatus:     resp_queue_inp.data = dmstatus;
+        dm::Hartinfo:     resp_queue_inp.data = hartinfo_aligned[selected_hart];
+        dm::AbstractCS:   resp_queue_inp.data = abstractcs;
+        dm::AbstractAuto: resp_queue_inp.data = abstractauto_q;
         // command is read-only
-        dm::Command:    resp_queue_data = '0;
+        dm::Command:    resp_queue_inp.data = '0;
         [(dm::ProgBuf0):ProgBufEnd]: begin
-          resp_queue_data = progbuf_q[dmi_req_i.addr[$clog2(dm::ProgBufSize)-1:0]];
+          resp_queue_inp.data = progbuf_q[dmi_req_i.addr[$clog2(dm::ProgBufSize)-1:0]];
           if (!cmdbusy_i) begin
             // check whether we need to re-execute the command (just give a cmd_valid)
             // range of autoexecprogbuf is 31:16
             cmd_valid_d = abstractauto_q.autoexecprogbuf[{1'b1, dmi_req_i.addr[3:0]}];
 
           // An abstract command was executing while one of the progbuf registers was read
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
-        dm::HaltSum0: resp_queue_data = haltsum0;
-        dm::HaltSum1: resp_queue_data = haltsum1;
-        dm::HaltSum2: resp_queue_data = haltsum2;
-        dm::HaltSum3: resp_queue_data = haltsum3;
+        dm::HaltSum0: resp_queue_inp.data = haltsum0;
+        dm::HaltSum1: resp_queue_inp.data = haltsum1;
+        dm::HaltSum2: resp_queue_inp.data = haltsum2;
+        dm::HaltSum3: resp_queue_inp.data = haltsum3;
         dm::SBCS: begin
-          resp_queue_data = sbcs_q;
+          resp_queue_inp.data = sbcs_q;
         end
         dm::SBAddress0: begin
-          resp_queue_data = sbaddr_q[31:0];
+          resp_queue_inp.data = sbaddr_q[31:0];
         end
         dm::SBAddress1: begin
-          resp_queue_data = sbaddr_q[63:32];
+          resp_queue_inp.data = sbaddr_q[63:32];
         end
         dm::SBData0: begin
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
             sbcs_d.sbbusyerror = 1'b1;
+            resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbdata_read_valid_o = (sbcs_q.sberror == '0);
-            resp_queue_data = sbdata_q[31:0];
+            resp_queue_inp.data = sbdata_q[31:0];
           end
         end
         dm::SBData1: begin
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
             sbcs_d.sbbusyerror = 1'b1;
+            resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
-            resp_queue_data = sbdata_q[63:32];
+            resp_queue_inp.data = sbdata_q[63:32];
           end
         end
         default:;
@@ -361,8 +369,11 @@ module dm_csrs #(
               // check whether we need to re-execute the command (just give a cmd_valid)
               cmd_valid_d = abstractauto_q.autoexecdata[autoexecdata_idx];
             //An abstract command was executing while one of the data registers was written
-            end else if (cmderr_q == dm::CmdErrNone) begin
-              cmderr_d = dm::CmdErrBusy;
+            end else begin
+              resp_queue_inp.resp = dm::DTM_BUSY;
+              if (cmderr_q == dm::CmdErrNone) begin
+                cmderr_d = dm::CmdErrBusy;
+              end
             end
           end
         end
@@ -385,8 +396,11 @@ module dm_csrs #(
           // reads during abstract command execution are not allowed
           if (!cmdbusy_i) begin
             cmderr_d = dm::cmderr_e'(~a_abstractcs.cmderr & cmderr_q);
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
         dm::Command: begin
@@ -396,8 +410,11 @@ module dm_csrs #(
             command_d = dm::command_t'(dmi_req_i.data);
           // if there was an attempted to write during a busy execution
           // and the cmderror field is zero set the busy error
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
         dm::AbstractAuto: begin
@@ -406,8 +423,11 @@ module dm_csrs #(
             abstractauto_d                 = 32'h0;
             abstractauto_d.autoexecdata    = 12'(dmi_req_i.data[dm::DataCount-1:0]);
             abstractauto_d.autoexecprogbuf = 16'(dmi_req_i.data[dm::ProgBufSize-1+16:16]);
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
         [(dm::ProgBuf0):ProgBufEnd]: begin
@@ -420,14 +440,18 @@ module dm_csrs #(
             // range of autoexecprogbuf is 31:16
             cmd_valid_d = abstractauto_q.autoexecprogbuf[{1'b1, dmi_req_i.addr[3:0]}];
           //An abstract command was executing while one of the progbuf registers was written
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
         dm::SBCS: begin
           // access while the SBA was busy
           if (sbbusy_i) begin
             sbcs_d.sbbusyerror = 1'b1;
+            resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbcs = dm::sbcs_t'(dmi_req_i.data);
             sbcs_d = sbcs;
@@ -440,6 +464,7 @@ module dm_csrs #(
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
             sbcs_d.sbbusyerror = 1'b1;
+            resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbaddr_d[31:0] = dmi_req_i.data;
             sbaddress_write_valid_o = (sbcs_q.sberror == '0);
@@ -449,6 +474,7 @@ module dm_csrs #(
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
             sbcs_d.sbbusyerror = 1'b1;
+            resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbaddr_d[63:32] = dmi_req_i.data;
           end
@@ -457,6 +483,7 @@ module dm_csrs #(
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
            sbcs_d.sbbusyerror = 1'b1;
+           resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbdata_d[31:0] = dmi_req_i.data;
             sbdata_write_valid_o = (sbcs_q.sberror == '0);
@@ -466,6 +493,7 @@ module dm_csrs #(
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
            sbcs_d.sbbusyerror = 1'b1;
+           resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbdata_d[63:32] = dmi_req_i.data;
           end
@@ -552,17 +580,17 @@ module dm_csrs #(
 
   // response FIFO
   prim_fifo_sync #(
-    .Width   (32),
+    .Width   ($bits(dmi_resp_o)),
     .Pass    (1'b0),
     .Depth   (2)
   ) i_fifo (
     .clk_i   ( clk_i                ),
     .rst_ni  ( dmi_rst_ni           ), // reset only when system is re-set
     .clr_i   ( 1'b0                 ),
-    .wdata_i ( resp_queue_data      ),
+    .wdata_i ( resp_queue_inp       ),
     .wvalid_i( dmi_req_valid_i      ),
     .wready_o( dmi_req_ready_o      ),
-    .rdata_o ( dmi_resp_o.data      ),
+    .rdata_o ( dmi_resp_o           ),
     .rvalid_o( dmi_resp_valid_o     ),
     .rready_i( dmi_resp_ready_i     ),
     .full_o  (                      ), // Unused