Merge branch 'devel'

lnls-dig · Nov 10, 2017 · baebec4 · baebec4
2 parents 2f99fc1 + b10a916
commit baebec4
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Showing 12 changed files with 158 additions and 51 deletions.
diff --git a/apps/halcsd/src/systemd/sysfiles/etc/systemd/system/[email protected] b/apps/halcsd/src/systemd/sysfiles/etc/systemd/system/[email protected]
@@ -2,6 +2,8 @@
 Description=HALCS server instance %I
 After=network-online.target
 Wants=network-online.target
+After=malamute.service
+Requires=malamute.service
 PartOf=halcs@%i.target
 
 [Service]

diff --git a/apps/halcsd/src/systemd/sysfiles/etc/systemd/system/[email protected] b/apps/halcsd/src/systemd/sysfiles/etc/systemd/system/[email protected]
@@ -2,6 +2,8 @@
 Description=HALCS server instance %I
 After=network-online.target
 Wants=network-online.target
+After=malamute.service
+Requires=malamute.service
 PartOf=halcs@%i.target
 
 [Service]

diff --git a/core/common/include/hw/wb_acq_core_regs.h b/core/common/include/hw/wb_acq_core_regs.h
@@ -3,7 +3,7 @@
 
   * File           : wb_acq_core_regs.h
   * Author         : auto-generated by wbgen2 from acq_core.wb
-  * Created        : Tue Aug 15 08:46:29 2017
+  * Created        : Wed Nov  1 10:46:18 2017
   * Standard       : ANSI C
 
     THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE acq_core.wb
@@ -153,11 +153,14 @@
 #define ACQ_CORE_SHOTS_NB_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
 #define ACQ_CORE_SHOTS_NB_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
 
-/* definitions for field: Reserved in reg: Number of shots */
-#define ACQ_CORE_SHOTS_RESERVED_MASK          WBGEN2_GEN_MASK(16, 16)
-#define ACQ_CORE_SHOTS_RESERVED_SHIFT         16
-#define ACQ_CORE_SHOTS_RESERVED_W(value)      WBGEN2_GEN_WRITE(value, 16, 16)
-#define ACQ_CORE_SHOTS_RESERVED_R(reg)        WBGEN2_GEN_READ(reg, 16, 16)
+/* definitions for field: MultiShot RAM size implemented in reg: Number of shots */
+#define ACQ_CORE_SHOTS_MULTISHOT_RAM_SIZE_IMPL WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: MultiShot RAM size in reg: Number of shots */
+#define ACQ_CORE_SHOTS_MULTISHOT_RAM_SIZE_MASK WBGEN2_GEN_MASK(17, 15)
+#define ACQ_CORE_SHOTS_MULTISHOT_RAM_SIZE_SHIFT 17
+#define ACQ_CORE_SHOTS_MULTISHOT_RAM_SIZE_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
+#define ACQ_CORE_SHOTS_MULTISHOT_RAM_SIZE_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
 
 /* definitions for register: Trigger address register */
 

diff --git a/core/sm_io/src/sm_io/c/chips/sm_ch_ad9510.c b/core/sm_io/src/sm_io/c/chips/sm_ch_ad9510.c
@@ -230,7 +230,9 @@ smch_err_e smch_ad9510_cfg_defaults (smch_ad9510_t *self)
     _smch_ad9510_write_8 (self, AD9510_REG_CLK_OPT, &data);
 
     /* Update registers */
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     SMCH_AD9510_WAIT_DFLT;
 
     /* Clock dividers OUT0 - OUT7
@@ -270,22 +272,29 @@ smch_err_e smch_ad9510_cfg_defaults (smch_ad9510_t *self)
     _smch_ad9510_write_8 (self, AD9510_REG_FUNCTION, &data);
 
     /* Update registers */
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     SMCH_AD9510_WAIT_DFLT;
 
     /* Software sync */
     data |= AD9510_FUNCTION_SYNC_REG;
     _smch_ad9510_write_8 (self, AD9510_REG_FUNCTION, &data);
 
     /* Update registers */
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     SMCH_AD9510_WAIT_DFLT;
 
     data &= ~AD9510_FUNCTION_SYNC_REG;
     _smch_ad9510_write_8 (self, AD9510_REG_FUNCTION, &data);
 
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
 
+err_reg_update:
 err_smpr_write:
     return err;
 }
@@ -302,10 +311,13 @@ smch_err_e smch_ad9510_set_pll_a_div (smch_ad9510_t *self, uint32_t *div)
     uint8_t data = AD9510_PLL_A_COUNTER_W(__div);
     _smch_ad9510_write_8 (self, AD9510_REG_PLL_A_COUNTER, &data);
 
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     /* Wait for reset to complete */
     SMCH_AD9510_WAIT_DFLT;
 
+err_reg_update:
 err_smpr_write:
     return err;
 }
@@ -354,10 +366,13 @@ smch_err_e smch_ad9510_set_pll_b_div (smch_ad9510_t *self, uint32_t *div)
     data = AD9510_PLL_B_LSB_COUNTER_W(__div);
     _smch_ad9510_write_8 (self, AD9510_REG_PLL_B_LSB_COUNTER, &data);
 
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     /* Wait for reset to complete */
     SMCH_AD9510_WAIT_DFLT;
 
+err_reg_update:
 err_smpr_write:
     return err;
 }
@@ -398,10 +413,13 @@ smch_err_e smch_ad9510_set_pll_prescaler (smch_ad9510_t *self, uint32_t *pre)
         AD9510_PLL_4_PRESCALER_P_W(__pre);
     _smch_ad9510_write_8 (self, AD9510_REG_PLL_4, &data);
 
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     /* Wait for reset to complete */
     SMCH_AD9510_WAIT_DFLT;
 
+err_reg_update:
     return err;
 }
 
@@ -437,10 +455,13 @@ smch_err_e smch_ad9510_set_pll_pdown (smch_ad9510_t *self, uint32_t *pdown)
         AD9510_PLL_4_PLL_PDOWN_W(__pdown);
     _smch_ad9510_write_8 (self, AD9510_REG_PLL_4, &data);
 
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     /* Wait for reset to complete */
     SMCH_AD9510_WAIT_DFLT;
 
+err_reg_update:
 err_smpr_write:
     return err;
 }
@@ -472,10 +493,13 @@ smch_err_e smch_ad9510_set_mux_status (smch_ad9510_t *self, uint32_t *mux)
         AD9510_PLL_2_MUX_SEL_W(__mux);
     _smch_ad9510_write_8 (self, AD9510_REG_PLL_2, &data);
 
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     /* Wait for reset to complete */
     SMCH_AD9510_WAIT_DFLT;
 
+err_reg_update:
 err_smpr_write:
     return err;
 }
@@ -506,10 +530,13 @@ smch_err_e smch_ad9510_set_r_div (smch_ad9510_t *self, uint32_t *div)
     data = AD9510_PLL_R_LSB_COUNTER_W(__div);
     _smch_ad9510_write_8 (self, AD9510_REG_PLL_R_LSB_COUNTER, &data);
 
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     /* Wait for reset to complete */
     SMCH_AD9510_WAIT_DFLT;
 
+err_reg_update:
 err_smpr_write:
     return err;
 }
@@ -554,10 +581,13 @@ smch_err_e smch_ad9510_set_cp_current (smch_ad9510_t *self, uint32_t *cp_current
             __cp_current/AD9510_PLL3_CP_CURRENT_MIN - 1);
     _smch_ad9510_write_8 (self, AD9510_REG_PLL_3, &data);
 
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     /* Wait for reset to complete */
     SMCH_AD9510_WAIT_DFLT;
 
+err_reg_update:
 err_smpr_write:
     return err;
 }
@@ -637,10 +667,13 @@ smch_err_e smch_ad9510_set_outputs (smch_ad9510_t *self, uint32_t *out_en)
         _smch_ad9510_write_8 (self, AD9510_REG_OUTPUT_START+i, &data);
     }
 
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     /* Wait for reset to complete */
     SMCH_AD9510_WAIT_DFLT;
 
+err_reg_update:
 err_smpr_write:
     return err;
 }
@@ -710,10 +743,13 @@ smch_err_e smch_ad9510_set_pll_clk_sel (smch_ad9510_t *self, uint32_t *clk_num)
 
     _smch_ad9510_write_8 (self, AD9510_REG_CLK_OPT, &data);
 
-    _smch_ad9510_reg_update (self);
+    err = _smch_ad9510_reg_update (self);
+    ASSERT_TEST(err == SMCH_SUCCESS, "Could not update AD9510 registers",
+            err_reg_update);
     /* Wait for reset to complete */
     SMCH_AD9510_WAIT_DFLT;
 
+err_reg_update:
 err_smpr_write:
     return err;
 }

diff --git a/core/sm_io/src/sm_io/c/modules/acq/sm_io_acq_core.c b/core/sm_io/src/sm_io/c/modules/acq/sm_io_acq_core.c
@@ -52,6 +52,24 @@ smio_acq_t * smio_acq_new (smio_t *parent, uint32_t num_samples_pre,
         self->num_chan = END_CHAN_ID;
     }
 
+    /* Get the number of multishot RAM size */
+    uint32_t multishot_ram_size_impl = 0;
+    GET_PARAM(parent, acq, 0x0, ACQ_CORE, SHOTS,
+            MULTISHOT_RAM_SIZE_IMPL, SINGLE_BIT_PARAM, multishot_ram_size_impl, 
+            NO_FMT_FUNC);
+    GET_PARAM(parent, acq, 0x0, ACQ_CORE, SHOTS,
+            MULTISHOT_RAM_SIZE, MULT_BIT_PARAM, self->multishot_ram_size, NO_FMT_FUNC);
+    if (!multishot_ram_size_impl) {
+        self->multishot_ram_size = ACQ_CORE_MULTISHOT_MEM_SIZE;
+    }
+    else if (self->multishot_ram_size == 0) {
+        DBE_DEBUG (DBG_SM_IO | DBG_LVL_WARN, "[sm_io:acq_core] Multishot RAM size is 0. "
+            "It will not be possible to perform multishot acquisitions for this module\n");
+    }
+
+    DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:acq_core] Multishot RAM size: %u\n",
+        self->multishot_ram_size);
+
     /* Initialize acq_buf */
     self->acq_buf = (acq_buf_t *) zmalloc ((sizeof *self->acq_buf) * self->num_chan);
     ASSERT_ALLOC (self->acq_buf, err_acq_buf_alloc);

diff --git a/core/sm_io/src/sm_io/c/modules/acq/sm_io_acq_core.h b/core/sm_io/src/sm_io/c/modules/acq/sm_io_acq_core.h
@@ -43,6 +43,7 @@ typedef struct {
     acq_params_t acq_params[END_CHAN_ID];   /* Parameters for each channel */
     uint32_t curr_chan;                     /* Current channel being acquired */
     uint32_t num_chan;                      /* Numbert of acquisition channels */
+    uint32_t multishot_ram_size;            /* Multishot RAM size, in acquistion words */
     acq_buf_t *acq_buf;                     /* Channel properties */
 } smio_acq_t;
 

diff --git a/core/sm_io/src/sm_io/c/modules/acq/sm_io_acq_exp.c b/core/sm_io/src/sm_io/c/modules/acq/sm_io_acq_exp.c
@@ -117,7 +117,7 @@ static int _acq_data_acquire (void *owner, void *args, void *ret)
     /* number of samples required is out of the maximum limit. Maixmum number of samples
      * in multishot mode is simply the maximum number of samples of the DPRAM. The DPRAM
      * size is calculated to fit the largest sample in the design, so we are safe. */
-    uint32_t max_samples_multishot = ACQ_CORE_MULTISHOT_MEM_SIZE;
+    uint32_t max_samples_multishot = acq->multishot_ram_size;
     if (((num_shots == ACQ_CORE_MIN_NUM_SHOTS) &&
             (num_samples_pre + num_samples_post > acq->acq_buf[chan].max_samples)) ||
             ((num_shots > ACQ_CORE_MIN_NUM_SHOTS) &&

diff --git a/examples/src/ad9510_ctl/c/ad9510_ctl.c b/examples/src/ad9510_ctl/c/ad9510_ctl.c
@@ -224,6 +224,15 @@ int main (int argc, char *argv [])
         }
     }
 
+    uint32_t r_div = 0;
+    halcs_client_err_e err = halcs_get_ad9510_r_div (halcs_client, service, &r_div);
+    if (err != HALCS_CLIENT_SUCCESS) {
+        fprintf (stderr, "[client:ad9510_ctl]: Error executing halcs_get_ad9510_r_div: error %s\n", halcs_client_err_str (err));
+    }
+    else {
+        fprintf (stdout, "[client:ad9510_ctl]: r_div = %u\n", r_div);
+    }
+
 err_halcs_client_new:
     halcs_client_destroy (&halcs_client);
 

diff --git a/examples/src/monit_amp/c/monit_amp.c b/examples/src/monit_amp/c/monit_amp.c
@@ -116,14 +116,14 @@ int main (int argc, char *argv [])
     }
 
     fprintf (stdout, "[client:monit_amp]: \n"
-              "monitoring amplitude ch0 = %u\n"
-              "monitoring amplitude ch1 = %u\n"
-              "monitoring amplitude ch2 = %u\n"
-              "monitoring amplitude ch3 = %u\n", 
-              dsp_data.amp_ch0,
-              dsp_data.amp_ch1,
-              dsp_data.amp_ch2,
-              dsp_data.amp_ch3);
+              "monitoring amplitude ch0 = %d\n"
+              "monitoring amplitude ch1 = %d\n"
+              "monitoring amplitude ch2 = %d\n"
+              "monitoring amplitude ch3 = %d\n", 
+              (int32_t) dsp_data.amp_ch0,
+              (int32_t) dsp_data.amp_ch1,
+              (int32_t) dsp_data.amp_ch2,
+              (int32_t) dsp_data.amp_ch3);
 
 err_get_monit_amp:
 err_halcs_client_new:

diff --git a/libs/halcsclient/src/halcsclient/c/halcs_client_rw_param.c b/libs/halcsclient/src/halcsclient/c/halcs_client_rw_param.c
@@ -337,6 +337,7 @@ halcs_client_err_e param_client_write_read_double (halcs_client_t *self, char *s
 zmsg_t *param_client_recv_timeout (halcs_client_t *self, char *service)
 {
     zmsg_t *msg = NULL;
+    const char *mlm_sender = NULL;
 
     /* Get poller and timeout from client */
     uint32_t timeout = halcs_client_get_timeout (self);
@@ -360,21 +361,32 @@ zmsg_t *param_client_recv_timeout (halcs_client_t *self, char *service)
     /* Check for activity socket */
     if (which == msgpipe) {
         mlm_client_t *mlm_client = halcs_get_mlm_client (self);
-        msg = mlm_client_recv (mlm_client);
-        const char *mlm_sender = mlm_client_sender (mlm_client);
-
-        /* Check if the message is for the service we are expecting.
-         * This can happen, for instance, if the same client is used to
-         * talk to more than 1 service. Depending on the server load,
-         * we can expect a message for a service 1, but receive the message
-         * for the service 2. One workaround to this is to use a single
-         * instance of the library per service */
-        if (!streq (mlm_sender, service)) {
-            /* free received message and warn caller */ 
-            zmsg_destroy (&msg);
-            DBE_DEBUG (DBG_LIB_CLIENT | DBG_LVL_FATAL, "[libclient] "
-                    "param_client_recv_timeout: Unexpected sender %s, waiting for %s\n",
-                     mlm_sender, service);
+
+        /* If we received an unexpected message, the receive buffer will 
+         * mostly likely have additonal messages that were sent by other 
+         * services. In this case, as we are acting as a synchronous protocol, 
+         * keep unpacking the receive buffer until our service string matches 
+         * the one we are expecting */
+        while (zsock_events (msgpipe) & ZMQ_POLLIN) {
+            msg = mlm_client_recv (mlm_client);
+            mlm_sender = mlm_client_sender (mlm_client);
+
+            /* Check if the message is for the service we are expecting.
+             * This can happen, for instance, if the same client is used to
+             * talk to more than 1 service. Depending on the server load,
+             * we can expect a message for a service 1, but receive the message
+             * for the service 2. One workaround to this is to use a single
+             * instance of the library per service */
+            if (!streq (mlm_sender, service)) {
+                /* free received message and warn caller */ 
+                zmsg_destroy (&msg);
+                DBE_DEBUG (DBG_LIB_CLIENT | DBG_LVL_FATAL, "[libclient] "
+                        "param_client_recv_timeout: Unexpected sender %s, waiting for %s\n",
+                         mlm_sender, service);
+            }
+            else {
+                break;
+            }
         }
     }
     else {