Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

CIC Decimation core re-written in VHDL #48

Draft
wants to merge 1 commit into
base: master
Choose a base branch
from
Draft

Conversation

augustofg
Copy link
Member

No description provided.

This is part of the ongoing effort of making all cores compatible
with open source HDL simulators like GHDL and NVC.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant