GitHub - hansungk/tsc-cpu: Simple in-order pipelined CPU implementation using TSC ISA for SNU ECE430.322 ComOrg

hansungk / tsc-cpu Public

Simple in-order pipelined CPU implementation using TSC ISA for SNU ECE430.322 ComOrg

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Name		Name	Last commit message	Last commit date
Latest commit History 55 Commits
.gitignore		.gitignore
DMA.v		DMA.v
Makefile		Makefile
RF.v		RF.v
TODO.txt		TODO.txt
alu.v		alu.v
alu_control.v		alu_control.v
branch_predictor.v		branch_predictor.v
cache.gtkw		cache.gtkw
cache.pdf		cache.pdf
cache.tex		cache.tex
cache.v		cache.v
constants.v		constants.v
control_unit.v		control_unit.v
cpu.v		cpu.v
cpu_TB.v		cpu_TB.v
datapath.v		datapath.v
dma.gtkw		dma.gtkw
dma.pdf		dma.pdf
dma.tex		dma.tex
dma_cyclesteal_1.PNG		dma_cyclesteal_1.PNG
dma_cyclesteal_2.PNG		dma_cyclesteal_2.PNG
dma_cyclestealing.wcfg		dma_cyclestealing.wcfg
external_device.v		external_device.v
fibo.asm		fibo.asm
forwarding_unit.v		forwarding_unit.v
hazard_unit.v		hazard_unit.v
inst_type.v		inst_type.v
ir.v		ir.v
memory.v		memory.v
opcodes.v		opcodes.v
pipelined.gtkw		pipelined.gtkw
pipelined.pdf		pipelined.pdf
pipelined.tex		pipelined.tex
testbench.asm		testbench.asm