remove master slave terminology from rocket-chip

src/main/scala/amba/ahb/AHBLite.scala

@@ -7,14 +7,14 @@ import org.chipsalliance.cde.config.Parameters
 import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
 
 class AHBLite()(implicit p: Parameters) extends LazyModule {
-  val node = AHBMasterAdapterNode(
-    masterFn = { mp => mp },
-    slaveFn  = { sp => sp.copy(lite = false) })
+  val node = AHBManagerAdapterNode(
+    managerFn = { mp => mp },
+    subordinateFn  = { sp => sp.copy(lite = false) })
 
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
-      require (edgeOut.slave.lite) // or else this adapter is pointless
+      require (edgeOut.subordinate.lite) // or else this adapter is pointless
 
       out.hmastlock.get := in.hlock.get
       in.hgrant.get := true.B

src/main/scala/amba/ahb/Bundles.scala

@@ -5,18 +5,18 @@ package freechips.rocketchip.amba.ahb
 import chisel3._
 import freechips.rocketchip.util._
 
-// Signal directions are from the master's point-of-view
-class AHBSlaveBundle(val params: AHBBundleParameters) extends Bundle
+// Signal directions are from the manager's point-of-view
+class AHBSubordinateBundle(val params: AHBBundleParameters) extends Bundle
 {
-  // Control signals from the arbiter to slave
+  // Control signals from the arbiter to subordinate
   val hmastlock = Output(Bool())
   val hsel      = Output(Bool())
 
   // Flow control signals (hreadyout=FALSE => hready=FALSE)
   val hready    = Output(Bool()) // from arbiter
   val hreadyout = Input(Bool())  // to arbiter
 
-  // A-phase signals from arbiter to slave
+  // A-phase signals from arbiter to subordinate
   val htrans    = Output(UInt(params.transBits.W))
   val hsize     = Output(UInt(params.sizeBits.W))
   val hburst    = Output(UInt(params.burstBits.W))
@@ -25,27 +25,27 @@ class AHBSlaveBundle(val params: AHBBundleParameters) extends Bundle
   val haddr     = Output(UInt(params.addrBits.W))
   val hauser    = BundleMap(params.requestFields)
 
-  // D-phase signals from arbiter to slave
+  // D-phase signals from arbiter to subordinate
   val hduser    = BundleMap(params.responseFields)
   val hwdata    = Output(UInt(params.dataBits.W))
 
-  // D-phase signals from slave to arbiter
+  // D-phase signals from subordinate to arbiter
   val hresp     = Input(UInt(params.hrespBits.W))
   val hrdata    = Input(UInt(params.dataBits.W))
 
   // Split signals
-  val hmaster   = if (params.lite) None else Some(Output(UInt(4.W)))
+  val hmanager   = if (params.lite) None else Some(Output(UInt(4.W)))
   val hsplit    = if (params.lite) None else Some(Input(UInt(16.W)))
 }
 
-class AHBMasterBundle(val params: AHBBundleParameters) extends Bundle
+class AHBManagerBundle(val params: AHBBundleParameters) extends Bundle
 {
-  // Control signals from master to arbiter
+  // Control signals from manager to arbiter
   val hmastlock = if (params.lite) Some(Output(Bool())) else None
   val hlock     = if (params.lite) None else Some(Output(Bool()))
   val hbusreq   = if (params.lite) None else Some(Output(Bool()))
 
-  // Flow control from arbiter to master
+  // Flow control from arbiter to manager
   val hgrant  = if (params.lite) None else Some(Input(Bool()))
   val hready  = Input(Bool())
 
@@ -54,7 +54,7 @@ class AHBMasterBundle(val params: AHBBundleParameters) extends Bundle
   def busreq(): Bool = if (params.lite) WireInit(true.B) else hbusreq.get
   def grant():  Bool = if (params.lite) WireInit(true.B) else hgrant.get
 
-  // A-phase signals from master to arbiter
+  // A-phase signals from manager to arbiter
   val htrans  = Output(UInt(params.transBits.W))
   val hsize   = Output(UInt(params.sizeBits.W))
   val hburst  = Output(UInt(params.burstBits.W))
@@ -63,21 +63,21 @@ class AHBMasterBundle(val params: AHBBundleParameters) extends Bundle
   val haddr   = Output(UInt(params.addrBits.W))
   val hauser  = BundleMap(params.requestFields)
 
-  // D-phase signals from master to arbiter
+  // D-phase signals from manager to arbiter
   val hduser    = BundleMap(params.responseFields)
   val hwdata  = Output(UInt(params.dataBits.W))
 
-  // D-phase response from arbiter to master
+  // D-phase response from arbiter to manager
   val hresp   = Input(UInt(params.hrespBits.W))
   val hrdata  = Input(UInt(params.dataBits.W))
 }
 
-object AHBSlaveBundle
+object AHBSubordinateBundle
 {
-  def apply(params: AHBBundleParameters) = new AHBSlaveBundle(params)
+  def apply(params: AHBBundleParameters) = new AHBSubordinateBundle(params)
 }
 
-object AHBMasterBundle
+object AHBManagerBundle
 {
-  def apply(params: AHBBundleParameters) = new AHBMasterBundle(params)
+  def apply(params: AHBBundleParameters) = new AHBManagerBundle(params)
 }

src/main/scala/amba/ahb/Monitor.scala

@@ -4,27 +4,27 @@ package freechips.rocketchip.amba.ahb
 
 import chisel3._
 
-case class AHBSlaveMonitorArgs(edge: AHBEdgeParameters)
+case class AHBSubordinateMonitorArgs(edge: AHBEdgeParameters)
 
-abstract class AHBSlaveMonitorBase(args: AHBSlaveMonitorArgs) extends Module
+abstract class AHBSubordinateMonitorBase(args: AHBSubordinateMonitorArgs) extends Module
 {
   val io = IO(new Bundle {
-    val in = Input(new AHBSlaveBundle(args.edge.bundle))
+    val in = Input(new AHBSubordinateBundle(args.edge.bundle))
   })
 
-  def legalize(bundle: AHBSlaveBundle, edge: AHBEdgeParameters, reset: Reset): Unit
+  def legalize(bundle: AHBSubordinateBundle, edge: AHBEdgeParameters, reset: Reset): Unit
   legalize(io.in, args.edge, reset)
 }
 
 
-case class AHBMasterMonitorArgs(edge: AHBEdgeParameters)
+case class AHBManagerMonitorArgs(edge: AHBEdgeParameters)
 
-abstract class AHBMasterMonitorBase(args: AHBMasterMonitorArgs) extends Module
+abstract class AHBManagerMonitorBase(args: AHBManagerMonitorArgs) extends Module
 {
   val io = IO(new Bundle {
-    val in = Input(new AHBMasterBundle(args.edge.bundle))
+    val in = Input(new AHBManagerBundle(args.edge.bundle))
   })
 
-  def legalize(bundle: AHBMasterBundle, edge: AHBEdgeParameters, reset: Reset): Unit
+  def legalize(bundle: AHBManagerBundle, edge: AHBEdgeParameters, reset: Reset): Unit
   legalize(io.in, args.edge, reset)
 }

src/main/scala/amba/ahb/Nodes.scala

@@ -10,80 +10,80 @@ import org.chipsalliance.cde.config.{Parameters, Field}
 import org.chipsalliance.diplomacy.ValName
 import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp, RenderedEdge, OutwardNode, InwardNode, SourceNode, SinkNode, IdentityNode, AdapterNode, MixedNexusNode, NexusNode}
 
-case object AHBSlaveMonitorBuilder extends Field[AHBSlaveMonitorArgs => AHBSlaveMonitorBase]
+case object AHBSubordinateMonitorBuilder extends Field[AHBSubordinateMonitorArgs => AHBSubordinateMonitorBase]
 
-// From Arbiter to Slave
-object AHBImpSlave extends SimpleNodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBSlaveBundle]
+// From Arbiter to Subordinate
+object AHBImpSubordinate extends SimpleNodeImp[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBEdgeParameters, AHBSubordinateBundle]
 {
-  def edge(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = AHBEdgeParameters(pd, pu, p, sourceInfo)
-  def bundle(e: AHBEdgeParameters) = AHBSlaveBundle(e.bundle)
-  def render(e: AHBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.slave.beatBytes * 8).toString)
+  def edge(pd: AHBManagerPortParameters, pu: AHBSubordinatePortParameters, p: Parameters, sourceInfo: SourceInfo) = AHBEdgeParameters(pd, pu, p, sourceInfo)
+  def bundle(e: AHBEdgeParameters) = AHBSubordinateBundle(e.bundle)
+  def render(e: AHBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.subordinate.beatBytes * 8).toString)
 
-  override def monitor(bundle: AHBSlaveBundle, edge: AHBEdgeParameters): Unit = {
-    edge.params.lift(AHBSlaveMonitorBuilder).foreach { builder =>
-      val monitor = Module(builder(AHBSlaveMonitorArgs(edge)))
+  override def monitor(bundle: AHBSubordinateBundle, edge: AHBEdgeParameters): Unit = {
+    edge.params.lift(AHBSubordinateMonitorBuilder).foreach { builder =>
+      val monitor = Module(builder(AHBSubordinateMonitorArgs(edge)))
       monitor.io.in := bundle
     }
   }
 
-  override def mixO(pd: AHBMasterPortParameters, node: OutwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBSlaveBundle]): AHBMasterPortParameters  =
-   pd.copy(masters = pd.masters.map  { c => c.copy (nodePath = node +: c.nodePath) })
-  override def mixI(pu: AHBSlavePortParameters, node: InwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBSlaveBundle]): AHBSlavePortParameters =
-   pu.copy(slaves  = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) })
+  override def mixO(pd: AHBManagerPortParameters, node: OutwardNode[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBSubordinateBundle]): AHBManagerPortParameters  =
+   pd.copy(managers = pd.managers.map  { c => c.copy (nodePath = node +: c.nodePath) })
+  override def mixI(pu: AHBSubordinatePortParameters, node: InwardNode[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBSubordinateBundle]): AHBSubordinatePortParameters =
+   pu.copy(subordinates  = pu.subordinates.map { m => m.copy (nodePath = node +: m.nodePath) })
 }
 
-case object AHBMasterMonitorBuilder extends Field[AHBMasterMonitorArgs => AHBMasterMonitorBase]
+case object AHBManagerMonitorBuilder extends Field[AHBManagerMonitorArgs => AHBManagerMonitorBase]
 
-// From Master to Arbiter
-object AHBImpMaster extends SimpleNodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBMasterBundle]
+// From Manager to Arbiter
+object AHBImpManager extends SimpleNodeImp[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBEdgeParameters, AHBManagerBundle]
 {
-  def edge(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = AHBEdgeParameters(pd, pu, p, sourceInfo)
-  def bundle(e: AHBEdgeParameters) = AHBMasterBundle(e.bundle)
-  def render(e: AHBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.slave.beatBytes * 8).toString)
+  def edge(pd: AHBManagerPortParameters, pu: AHBSubordinatePortParameters, p: Parameters, sourceInfo: SourceInfo) = AHBEdgeParameters(pd, pu, p, sourceInfo)
+  def bundle(e: AHBEdgeParameters) = AHBManagerBundle(e.bundle)
+  def render(e: AHBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.subordinate.beatBytes * 8).toString)
 
-  override def monitor(bundle: AHBMasterBundle, edge: AHBEdgeParameters): Unit = {
-    edge.params.lift(AHBMasterMonitorBuilder).foreach { builder =>
-      val monitor = Module(builder(AHBMasterMonitorArgs(edge)))
+  override def monitor(bundle: AHBManagerBundle, edge: AHBEdgeParameters): Unit = {
+    edge.params.lift(AHBManagerMonitorBuilder).foreach { builder =>
+      val monitor = Module(builder(AHBManagerMonitorArgs(edge)))
       monitor.io.in := bundle
     }
   }
 
-  override def mixO(pd: AHBMasterPortParameters, node: OutwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBMasterBundle]): AHBMasterPortParameters  =
-   pd.copy(masters = pd.masters.map  { c => c.copy (nodePath = node +: c.nodePath) })
-  override def mixI(pu: AHBSlavePortParameters, node: InwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBMasterBundle]): AHBSlavePortParameters =
-   pu.copy(slaves  = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) })
+  override def mixO(pd: AHBManagerPortParameters, node: OutwardNode[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBManagerBundle]): AHBManagerPortParameters  =
+   pd.copy(managers = pd.managers.map  { c => c.copy (nodePath = node +: c.nodePath) })
+  override def mixI(pu: AHBSubordinatePortParameters, node: InwardNode[AHBManagerPortParameters, AHBSubordinatePortParameters, AHBManagerBundle]): AHBSubordinatePortParameters =
+   pu.copy(subordinates  = pu.subordinates.map { m => m.copy (nodePath = node +: m.nodePath) })
 }
 
 // Nodes implemented inside modules
-case class AHBMasterSourceNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends SourceNode(AHBImpMaster)(portParams)
-case class AHBSlaveSourceNode(portParams: Seq[AHBMasterPortParameters])(implicit valName: ValName) extends SourceNode(AHBImpSlave)(portParams)
-case class AHBMasterSinkNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends SinkNode(AHBImpMaster)(portParams)
-case class AHBSlaveSinkNode(portParams: Seq[AHBSlavePortParameters])(implicit valName: ValName) extends SinkNode(AHBImpSlave)(portParams)
-case class AHBMasterIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImpMaster)()
-case class AHBSlaveIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImpSlave)()
-
-case class AHBMasterAdapterNode(
-  masterFn:       AHBMasterPortParameters => AHBMasterPortParameters,
-  slaveFn:        AHBSlavePortParameters  => AHBSlavePortParameters)(
+case class AHBManagerSourceNode(portParams: Seq[AHBManagerPortParameters])(implicit valName: ValName) extends SourceNode(AHBImpManager)(portParams)
+case class AHBSubordinateSourceNode(portParams: Seq[AHBManagerPortParameters])(implicit valName: ValName) extends SourceNode(AHBImpSubordinate)(portParams)
+case class AHBManagerSinkNode(portParams: Seq[AHBSubordinatePortParameters])(implicit valName: ValName) extends SinkNode(AHBImpManager)(portParams)
+case class AHBSubordinateSinkNode(portParams: Seq[AHBSubordinatePortParameters])(implicit valName: ValName) extends SinkNode(AHBImpSubordinate)(portParams)
+case class AHBManagerIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImpManager)()
+case class AHBSubordinateIdentityNode()(implicit valName: ValName) extends IdentityNode(AHBImpSubordinate)()
+
+case class AHBManagerAdapterNode(
+  managerFn:       AHBManagerPortParameters => AHBManagerPortParameters,
+  subordinateFn:        AHBSubordinatePortParameters  => AHBSubordinatePortParameters)(
   implicit valName: ValName)
-  extends AdapterNode(AHBImpMaster)(masterFn, slaveFn)
+  extends AdapterNode(AHBImpManager)(managerFn, subordinateFn)
 
-case class AHBSlaveAdapterNode(
-  masterFn:       AHBMasterPortParameters => AHBMasterPortParameters,
-  slaveFn:        AHBSlavePortParameters  => AHBSlavePortParameters)(
+case class AHBSubordinateAdapterNode(
+  managerFn:       AHBManagerPortParameters => AHBManagerPortParameters,
+  subordinateFn:        AHBSubordinatePortParameters  => AHBSubordinatePortParameters)(
   implicit valName: ValName)
-  extends AdapterNode(AHBImpMaster)(masterFn, slaveFn)
+  extends AdapterNode(AHBImpManager)(managerFn, subordinateFn)
 
-// From Master to Arbiter to Slave
+// From Manager to Arbiter to Subordinate
 case class AHBArbiterNode(
-  masterFn:       Seq[AHBMasterPortParameters] => AHBMasterPortParameters,
-  slaveFn:        Seq[AHBSlavePortParameters]  => AHBSlavePortParameters)(
+  managerFn:       Seq[AHBManagerPortParameters] => AHBManagerPortParameters,
+  subordinateFn:        Seq[AHBSubordinatePortParameters]  => AHBSubordinatePortParameters)(
   implicit valName: ValName)
-  extends MixedNexusNode(AHBImpMaster, AHBImpSlave)(masterFn, slaveFn)
+  extends MixedNexusNode(AHBImpManager, AHBImpSubordinate)(managerFn, subordinateFn)
 
-// Combine multiple Slaves into one logical Slave (suitable to attach to an Arbiter)
+// Combine multiple Subordinates into one logical Subordinate (suitable to attach to an Arbiter)
 case class AHBFanoutNode(
-  masterFn:       Seq[AHBMasterPortParameters] => AHBMasterPortParameters,
-  slaveFn:        Seq[AHBSlavePortParameters]  => AHBSlavePortParameters)(
+  managerFn:       Seq[AHBManagerPortParameters] => AHBManagerPortParameters,
+  subordinateFn:        Seq[AHBSubordinatePortParameters]  => AHBSubordinatePortParameters)(
   implicit valName: ValName)
-  extends NexusNode(AHBImpSlave)(masterFn, slaveFn)
+  extends NexusNode(AHBImpSubordinate)(managerFn, subordinateFn)

src/main/scala/amba/ahb/Parameters.scala

@@ -15,7 +15,7 @@ import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase}
 
 import scala.math.{max, min}
 
-case class AHBSlaveParameters(
+case class AHBSubordinateParameters(
   address:       Seq[AddressSet],
   resources:     Seq[Resource] = Nil,
   regionType:    RegionType.T  = RegionType.GET_EFFECTS,
@@ -47,39 +47,39 @@ case class AHBSlaveParameters(
   }
 }
 
-case class AHBSlavePortParameters(
-  slaves:     Seq[AHBSlaveParameters],
+case class AHBSubordinatePortParameters(
+  subordinates:     Seq[AHBSubordinateParameters],
   beatBytes:  Int,
   lite:       Boolean,
   responseFields: Seq[BundleFieldBase] = Nil,
   requestKeys:    Seq[BundleKeyBase]   = Nil)
 {
-  require (!slaves.isEmpty)
+  require (!subordinates.isEmpty)
   require (isPow2(beatBytes))
 
-  val minMaxTransfer = slaves.map(_.minMaxTransfer).min // useful for fragmentation
-  val maxTransfer = slaves.map(_.maxTransfer).max
-  val maxAddress = slaves.map(_.maxAddress).max
+  val minMaxTransfer = subordinates.map(_.minMaxTransfer).min // useful for fragmentation
+  val maxTransfer = subordinates.map(_.maxTransfer).max
+  val maxAddress = subordinates.map(_.maxAddress).max
 
   // Check the link is not pointlessly wide
   require (maxTransfer >= beatBytes)
   // Check that the link can be implemented in AHB
   require (maxTransfer <= beatBytes * AHBParameters.maxTransfer)
 
   // Require disjoint ranges for addresses
-  slaves.combinations(2).foreach { case Seq(x,y) =>
+  subordinates.combinations(2).foreach { case Seq(x,y) =>
     x.address.foreach { a => y.address.foreach { b =>
       require (!a.overlaps(b))
     } }
   }
 }
 
-case class AHBMasterParameters(
+case class AHBManagerParameters(
   name:     String,
   nodePath: Seq[BaseNode] = Nil)
 
-case class AHBMasterPortParameters(
-  masters: Seq[AHBMasterParameters],
+case class AHBManagerPortParameters(
+  managers: Seq[AHBManagerParameters],
   requestFields: Seq[BundleFieldBase] = Nil,
   responseKeys:  Seq[BundleKeyBase]   = Nil)
 
@@ -118,20 +118,20 @@ object AHBBundleParameters
   def union(x: Seq[AHBBundleParameters]) =
     if (x.isEmpty) emptyBundleParams else x.tail.foldLeft(x.head)((x,y) => x.union(y))
 
-  def apply(master: AHBMasterPortParameters, slave: AHBSlavePortParameters) =
+  def apply(manager: AHBManagerPortParameters, subordinate: AHBSubordinatePortParameters) =
     new AHBBundleParameters(
-      addrBits = log2Up(slave.maxAddress+1),
-      dataBits = slave.beatBytes * 8,
-      requestFields  = BundleField.accept(master.requestFields, slave.requestKeys),
-      responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
-      lite  = slave.lite)
+      addrBits = log2Up(subordinate.maxAddress+1),
+      dataBits = subordinate.beatBytes * 8,
+      requestFields  = BundleField.accept(manager.requestFields, subordinate.requestKeys),
+      responseFields = BundleField.accept(subordinate.responseFields, manager.responseKeys),
+      lite  = subordinate.lite)
 }
 
 case class AHBEdgeParameters(
-  master: AHBMasterPortParameters,
-  slave:  AHBSlavePortParameters,
+  manager: AHBManagerPortParameters,
+  subordinate:  AHBSubordinatePortParameters,
   params: Parameters,
   sourceInfo: SourceInfo)
 {
-  val bundle = AHBBundleParameters(master, slave)
+  val bundle = AHBBundleParameters(manager, subordinate)
 }

src/main/scala/amba/ahb/RegisterRouter.scala

@@ -18,8 +18,8 @@ import freechips.rocketchip.util.MaskGen
 import scala.math.min
 
 case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)
-  extends SinkNode(AHBImpSlave)(Seq(AHBSlavePortParameters(
-    Seq(AHBSlaveParameters(
+  extends SinkNode(AHBImpSubordinate)(Seq(AHBSubordinatePortParameters(
+    Seq(AHBSubordinateParameters(
       address       = Seq(address),
       executable    = executable,
       supportsWrite = TransferSizes(1, min(address.alignment.toInt, beatBytes * AHBParameters.maxTransfer)),

src/main/scala/amba/ahb/SRAM.scala

@@ -22,8 +22,8 @@ class AHBRAM(
     errors: Seq[AddressSet] = Nil)
   (implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName)
 {
-  val node = AHBSlaveSinkNode(Seq(AHBSlavePortParameters(
-    Seq(AHBSlaveParameters(
+  val node = AHBSubordinateSinkNode(Seq(AHBSubordinatePortParameters(
+    Seq(AHBSubordinateParameters(
       address       = List(address) ++ errors,
       resources     = resources,
       regionType    = if (cacheable) RegionType.UNCACHED else RegionType.IDEMPOTENT,