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Sync dev to master #3675
Sync dev to master #3675
Commits on Sep 26, 2023
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Commits on Sep 27, 2023
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Commits on Oct 2, 2023
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Commits on Oct 7, 2023
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Fix the missing flow argument in TileLink/ToAXI4 (#3505)
`flow` must be explicitly passed to `Queue.irrevocable` to avoid mismatching the arguments.
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Fix the missing DontCare in TileLink Edges/Delayer (#3504)
* add DontCare for user/echo bits in Channel A/C/D * add DontCare for messages without any data payload
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Commits on Oct 11, 2023
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Bump flake dependencies (#3506)
* bump flake * remove legacy firtool option
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Commits on Oct 16, 2023
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Commits on Oct 17, 2023
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Commits on Oct 18, 2023
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Commits on Oct 19, 2023
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Commits on Oct 20, 2023
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Commits on Oct 25, 2023
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Commits on Nov 1, 2023
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Merge pull request #3516 from chipsalliance/jerryz123-patch-2
Fix CSRIO bidir connection
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Commits on Nov 2, 2023
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Commits on Nov 7, 2023
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Merge pull request #3520 from abejgonzalez/delay-queue
Add DelayQueue
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Commits on Nov 14, 2023
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Fix r_pte update condition when S2 PTE cache hit (#3525) (#3526)
Co-authored-by: Sihao Liu <[email protected]>
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Commits on Nov 15, 2023
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Merge pull request #3507 from chipsalliance/chisel_source
Support RocketChip build Chisel from source
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Commits on Nov 16, 2023
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Merge pull request #3530 from chipsalliance/chisel5p1
Bump to Chisel 5.1
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Commits on Nov 17, 2023
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Commits on Nov 23, 2023
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Commits on Nov 25, 2023
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Merge pull request #3537 from chipsalliance/vec-hotfix
Support vector-units w/o L1D$ access
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Commits on Nov 28, 2023
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Commits on Dec 16, 2023
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Commits on Dec 20, 2023
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Commits on Dec 27, 2023
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Commits on Dec 28, 2023
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Commits on Jan 3, 2024
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Commits on Jan 4, 2024
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Commits on Jan 5, 2024
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Merge pull request #3553 from poemonsense/fix-outer-argument
Remove the unused outer argument in HellaCacheBundle
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Commits on Jan 8, 2024
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Commits on Jan 9, 2024
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Merge pull request #3490 from chipsalliance/clusters2
Support Tile Clusters (tree-like hierarchies)
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Commits on Jan 20, 2024
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Add hardware ROB debugger to trace register writeback values
(Only for integer registers)
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Commits on Jan 22, 2024
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Commits on Jan 23, 2024
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Merge pull request #3561 from SpriteOvO/fix-chisel-deprecated-api-dev
Fix Chisel deprecated APIs
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Commits on Jan 25, 2024
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Commits on Jan 26, 2024
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Update src/main/scala/rocket/RocketCore.scala
Co-authored-by: Jerry Zhao <[email protected]>
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Update src/main/scala/rocket/RocketCore.scala
Co-authored-by: Jerry Zhao <[email protected]>
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Commits on Jan 29, 2024
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Merge pull request #3566 from chipsalliance/sync
Sync master into dev
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Merge pull request #3565 from chipsalliance/no-rr
Remove deprecated RegisterRouter APIs
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Merge pull request #3560 from joey0320/trace-wb-dev
Add hardware debug ROB
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Commits on Feb 1, 2024
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Commits on Feb 2, 2024
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Commits on Feb 12, 2024
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Merge pull request #3539 from chipsalliance/rocc-csr-fence
Fence for RoCC on rocc-csr writes
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Commits on Feb 13, 2024
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Merge pull request #3568 from chipsalliance/pmas
Modularize PMA-checking functionality
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Commits on Feb 15, 2024
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Commits on Feb 20, 2024
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Merge pull request #3549 from tymcauley/waiveall-axi4-xbar
Fix AXI4 Xbar elaboration error due to missing fields
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Commits on Feb 23, 2024
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Commits on Feb 25, 2024
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Merge pull request #3572 from chipsalliance/tl-sorted
Use sortedSlaves in some TL helpers
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Merge pull request #3573 from chipsalliance/no-more-sbus
remove depending on explicit SBUS
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Commits on Feb 26, 2024
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Merge pull request #3574 from chipsalliance/clean-up-resource-api
Prepare to purge resource API
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Commits on Feb 27, 2024
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Merge pull request #3575 from chipsalliance/no-more-xbus
Purge xbus in BaseSubsystem
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Commits on Feb 28, 2024
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Merge pull request #3577 from chipsalliance/fifo-identity
FIFOFixer should be identity when no clients may request Fifo
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Merge pull request #3567 from richardyrh/rocc-slave
Add slave node to RoCC
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Move diplomacy to standalone library absorbing aop
Splits out the aop and diplomacy modules into a standalone library. Adds the new library as a dependency and updates the in-tree diplomacy and aop modules to reference the new library with deprecation warnings.
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Commits on Feb 29, 2024
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Commits on Mar 1, 2024
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Merge pull request #3578 from chipsalliance/full-mul
Support pulling out full imul response
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Commits on Mar 4, 2024
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Merge pull request #3580 from tymcauley/remove-sfc-options
Delete SFC RegisteredLibrary file
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Commits on Mar 6, 2024
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Update diplomacy dependency to track master
Updates the diplomacy dependency submodule to track chipsalliance/diplomacy master branch.
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Commits on Mar 8, 2024
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Merge pull request #3571 from lordspacehog/aswehla/standalone_diplomacy
Move diplomacy to standalone library absorbing aop
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Commits on Mar 11, 2024
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Merge pull request #3583 from chipsalliance/diplomacy-bump
bump diplomacy and switch to diplomacy/master
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Commits on Mar 12, 2024
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Commits on Mar 13, 2024
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Commits on Mar 15, 2024
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Merge pull request #3589 from chipsalliance/precise_tlb_perms
Support managers with < pageSize alignment
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Merge pull request #3588 from chipsalliance/tlb_port
Generalize tlb_port | improve NBDcache performance
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Commits on Mar 16, 2024
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Commits on Mar 18, 2024
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Port AMBA to standalone diplomacy
Updates AMBA to use standalone diplomacy module directly. Fixes a small issue with builds using chisel source for diplomacy module.
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Commits on Mar 19, 2024
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Merge pull request #3592 from Zephyr-Computing-Systems/aswehla/amba_d…
…iplomacy_update Make AMBA package importing explicit
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Commits on Mar 20, 2024
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Merge pull request #3598 from chipsalliance/fix_s1_data
Fix s1_data when coreDataBits > xLen
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Merge pull request #3595 from chipsalliance/tlfrag-assert
Allow TLFragmenter to fragment from non-probable masters
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Merge pull request #3600 from chipsalliance/sync
Sync master into dev
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Migrate diplomacy imports to standalone diplomacy
Updates diplomacy imports to explicitly use standalone diplomacy module.
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Merge pull request #3602 from Zephyr-Computing-Systems/aswehla/update…
…_diplomacy_imports Migrate diplomacy imports to standalone diplomacy
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Merge pull request #3605 from chipsalliance/debug-fix
Fix chisel3.experimental imports in debug/Periphery
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Merge pull request #3606 from chipsalliance/plic-order
Fix connection order of meip/seip to plic
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Merge pull request #3608 from chipsalliance/tile-int-fix
Fix tile interrupt sources
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Commits on Apr 10, 2024
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Update SRAM.scala to improve perf on non-full sized reads
Change a_sublane to not count sublanes if it's a read. Reads return full data width, no matter if the A channel size is not the data width
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Merge pull request #3614 from Kevin99214/master
Update SRAM.scala to improve perf on non-full sized reads
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Merge pull request #3613 from OpenXiangShan/illegal_rvc
Add illegal instruction detection to RVC decoder
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Merge pull request #3625 from chipsalliance/ptw_gf
PTW: traverse check GPA bits higher than HGATP mode only if valid
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Merge pull request #3624 from chipsalliance/mhtinst
Hypervisor: drive mtinst/htinst
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Merge pull request #3626 from chipsalliance/width-fix
Fix extraction-width warnings
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Commits on May 11, 2024
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Merge pull request #3628 from joonho3020/plic-domain-name
Suggest name for plic domain
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Commits on May 17, 2024
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Merge pull request #3599 from chipsalliance/ifv
Interface to vector units
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Merge pull request #3631 from chipsalliance/cp_fpu
Minor FPU imropvements
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Update APBtoTL scala to not flip apb address when doing conversion
APB address is getting bitwise flipped to get TL address which then immediately fails the assertion that checks they are the same. Revert line that does the flip to previous version.
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Add IO Connections for Custom User Field in TL Channels within Xbar
module Please refer to the issue page below. ucb-bar/chipyard#1888
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Merge pull request #3634 from Kevin99214/APBToTLfix
Update APBtoTL scala to not flip apb address when doing conversion
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Merge pull request #3639 from chipsalliance/named_domains
Name the ClockDomains
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Commits on Jun 5, 2024
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Merge pull request #3642 from chipsalliance/empty_diplomacy
Move clocking/resources out of diplomacy subpackage
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Commits on Jun 13, 2024
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Merge pull request #3648 from chipsalliance/tile_int_domain
Interrupts coming outwards from the Tile should cross into a toPlicDomain
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Merge pull request #3641 from chipsalliance/naming
Set parameterized desiredName on many system componets
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Merge pull request #3651 from chipsalliance/ptw_leaf
PTW: traverse check GPA bits higher than HGATP mode only if leaf
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Merge pull request #3652 from chipsalliance/rvv_isastrs
Allow non-V implementations of vector units, with Zve/Zvl extensions
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Merge pull request #3654 from Kevin99214/NewSubsystemConfigFragments
Adding new config fragments to Rocket-chip subsystem Config.scala
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Merge pull request #3655 from chipsalliance/split-configs
Move rocket-related config fragments to rocket/Configs.scala
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Add IO Connections for Custom User Field in TL Channels within Xbar
DontCare should come first before waiveAll so that matching userfield bewteen bundles can be connected Please refer to the issue page below. ucb-bar/chipyard#1888
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Fix for compilation error in PhysicallFilter
I think this module is not tested during Chisel version is updated. I fixed compiler error by chiselTypeOf
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Merge pull request #3637 from ksungkeun84/master
Add IO Connections for Custom User Field in TL Channels within Xbar
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Commits on Jul 23, 2024
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Merge pull request #3659 from chipsalliance/zvfh
Fix support for vector units with Zvfh
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Commits on Aug 8, 2024
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Merge pull request #3665 from chipsalliance/v_exts
Support vector extensions
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Commits on Aug 12, 2024
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Merge pull request #3670 from chipsalliance/vec_bypasses
Prevent bypasses from vector instructions | fix vsets
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