Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

remove CompileOption in tilelink Broadcast #3457

Closed
wants to merge 1 commit into from
Closed
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 3 additions & 4 deletions src/main/scala/tilelink/Broadcast.scala
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,6 @@ package freechips.rocketchip.tilelink

import chisel3._
import chisel3.util._
import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
Expand Down Expand Up @@ -119,7 +118,7 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz
val d_what = out.d.bits.source(d_high+1, d_high)
val d_drop = d_what === DROP
val d_hasData = edgeOut.hasData(out.d.bits)
val d_normal = Wire(in.d)
val d_normal = Wire(chiselTypeOf(in.d))
val (d_first, d_last, _) = edgeIn.firstlast(d_normal)
val d_trackerOH = VecInit(trackers.map { t => t.need_d && t.source === d_normal.bits.source }).asUInt holdUnless d_first

Expand Down Expand Up @@ -179,8 +178,8 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz
in.c.bits.param === TLPermissions.BtoB)
}

val releaseack = Wire(in.d)
val putfull = Wire(out.a)
val releaseack = Wire(chiselTypeOf(in.d))
val putfull = Wire(chiselTypeOf(out.a))

in.c.ready := c_probeack || Mux(c_release, releaseack.ready, putfull.ready)

Expand Down
Loading