New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[TestDriver.v] Set initial `clock = 1'b1;` #3000

Open

Waxpple wants to merge 1 commit into chipsalliance:master from Waxpple:master

Commits on Jun 23, 2022

Set initial clock = 1'b1;

Set `clock = 1'b1;` to avoid the first reset signal only using half of the clock cycle.
If want to avoid the first reset cycle using only half clock period causing timing violation, modify `TestDriver.v` like this:
![image](https://user-images.githubusercontent.com/20642651/175191673-3447a393-b064-4dc5-8584-9fd30480d166.png)

The waveform will be:
![image](https://user-images.githubusercontent.com/20642651/175193123-431b326b-e706-4f40-ab6b-71150b49065a.png)

The original testbench will look like this:
![image](https://user-images.githubusercontent.com/20642651/175190617-b13a16eb-2187-4cf1-8bc5-c6d5c9d23c8b.png)
The waveform will be
![image](https://user-images.githubusercontent.com/20642651/175191639-2ae13e6b-ef4b-4026-8282-2dd4f03bd8b5.png)

Waxpple authored Jun 23, 2022