Fix vector debug trace

chipsalliance · May 17, 2024 · d92922a · d92922a
1 parent 22cc8aa
commit d92922a
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -904,7 +904,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
       val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard)
       val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U))
 
-      io.vector.foreach { v => when (v.wb.retire && !wb_reg_set_vconfig) {
+      io.vector.foreach { v => when (v.wb.retire) {
         should_wb := v.wb.rob_should_wb
         has_wb := false.B
         wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7))