Merge remote-tracking branch 'origin/dev' into ifv

src/main/scala/rocket/CSR.scala

@@ -287,6 +287,7 @@ class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle
   val pc = Input(UInt(vaddrBitsExtended.W))
   val tval = Input(UInt(vaddrBitsExtended.W))
   val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W))
+  val mhtinst_read_pseudo = Input(Bool())
   val gva = Input(Bool())
   val time = Output(UInt(xLen.W))
   val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W))
@@ -580,6 +581,12 @@ class CSRFile(
   val reg_vxsat = usingVector.option(Reg(Bool()))
   val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W)))
 
+  val reg_mtinst_read_pseudo = Reg(Bool())
+  val reg_htinst_read_pseudo = Reg(Bool())
+  // XLEN=32: 0x00002000
+  // XLEN=64: 0x00003000
+  val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W)))
+
   val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W))
   io.inhibit_cycle := reg_mcountinhibit(0)
   val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2))
@@ -799,7 +806,7 @@ class CSRFile(
   val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2))
 
   if (usingHypervisor) {
-    read_mapping += CSRs.mtinst -> 0.U
+    read_mapping += CSRs.mtinst -> read_mtinst
     read_mapping += CSRs.mtval2 -> reg_mtval2
 
     val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0)
@@ -815,7 +822,7 @@ class CSRFile(
     read_mapping += CSRs.hgeie -> 0.U
     read_mapping += CSRs.hgeip -> 0.U
     read_mapping += CSRs.htval -> reg_htval
-    read_mapping += CSRs.htinst -> 0.U
+    read_mapping += CSRs.htinst -> read_htinst
     read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt
     if (xLen == 32)
       read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32)
@@ -1063,6 +1070,7 @@ class CSRFile(
       reg_scause := cause
       reg_stval := tval
       reg_htval := io.htval
+      reg_htinst_read_pseudo := io.mhtinst_read_pseudo
       reg_mstatus.spie := reg_mstatus.sie
       reg_mstatus.spp := reg_mstatus.prv
       reg_mstatus.sie := false.B
@@ -1075,6 +1083,7 @@ class CSRFile(
       reg_mcause := cause
       reg_mtval := tval
       reg_mtval2 := io.htval
+      reg_mtinst_read_pseudo := io.mhtinst_read_pseudo
       reg_mstatus.mpie := reg_mstatus.mie
       reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
       reg_mstatus.mie := false.B
@@ -1400,6 +1409,10 @@ class CSRFile(
       when (decoded_addr(CSRs.htval))      { reg_htval := wdata }
       when (decoded_addr(CSRs.mtval2))     { reg_mtval2 := wdata }
 
+      val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12))
+      when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo }
+      when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo }
+
       when (decoded_addr(CSRs.vsstatus)) {
         val new_vsstatus = wdata.asTypeOf(new MStatus())
         reg_vsstatus.sie := new_vsstatus.sie

src/main/scala/rocket/Frontend.scala

@@ -55,6 +55,7 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
   val sfence = Valid(new SFenceReq)
   val resp = Flipped(Decoupled(new FrontendResp))
   val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W)))
+  val gpa_is_pte = Input(Bool())
   val btb_update = Valid(new BTBUpdate)
   val bht_update = Valid(new BHTUpdate)
   val ras_update = Valid(new RASUpdate)
@@ -243,7 +244,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
       val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ
       val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL
       val rvcJump = bits === Instructions.C_J || rvcJAL
-      val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen).bImm.asSInt, new RVCDecoder(bits, xLen).jImm.asSInt)
+      val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt)
       val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U
       val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7)
       val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U
@@ -351,9 +352,11 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
   // supply guest physical address to commit stage
   val gpa_valid = Reg(Bool())
   val gpa = Reg(UInt(vaddrBitsExtended.W))
+  val gpa_is_pte = Reg(Bool())
   when (fq.io.enq.fire && s2_tlb_resp.gf.inst) {
     when (!gpa_valid) {
       gpa := s2_tlb_resp.gpa
+      gpa_is_pte := s2_tlb_resp.gpa_is_pte
     }
     gpa_valid := true.B
   }
@@ -362,6 +365,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
   }
   io.cpu.gpa.valid := gpa_valid
   io.cpu.gpa.bits := gpa
+  io.cpu.gpa_is_pte := gpa_is_pte
 
   // performance events
   io.cpu.perf.acquire := icache.io.perf.acquire

src/main/scala/rocket/PTW.scala

@@ -695,7 +695,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
       when (do_both_stages && !stage2) { do_switch := true.B }
       count := count + 1.U
     }.otherwise {
-      val gf = stage2 && !stage2_final && !pte.ur()
+      val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.v && pte.reserved_for_future === 0.U && invalid_gpa)
       val ae = pte.v && invalid_paddr
       val pf = pte.v && pte.reserved_for_future =/= 0.U
       val success = pte.v && !ae && !pf && !gf

src/main/scala/rocket/RVC.scala

@@ -16,7 +16,7 @@ class ExpandedInstruction extends Bundle {
   val rs3 = UInt(5.W)
 }
 
-class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false) {
+class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) {
   def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
     val res = Wire(new ExpandedInstruction)
     res.bits := bits
@@ -153,20 +153,56 @@ class RVCDecoder(x: UInt, xLen: Int, useAddiForMv: Boolean = false) {
     val s = q0 ++ q1 ++ q2 ++ q3
     s(Cat(x(1,0), x(15,13)))
   }
+
+  def q0_ill = {
+    def allz = !(x(12, 2).orR)
+    def fld = if (fLen >= 64) false.B else true.B
+    def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
+    def fsd = if (fLen >= 64) false.B else true.B
+    def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
+    Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32)
+  }
+
+  def q1_ill = {
+    def rd0 = if (xLen == 32) false.B else rd === 0.U
+    def immz = !(x(12) | x(6, 2).orR)
+    def arith_res = x(12, 10).andR && (if (xLen == 32) true.B else x(6) === 1.U)
+    Seq(false.B, rd0, false.B, immz, arith_res, false.B, false.B, false.B)
+  }
+
+  def q2_ill = {
+    def fldsp = if (fLen >= 64) false.B else true.B
+    def rd0 = rd === 0.U
+    def flwsp = if (xLen == 64) rd0 else if (fLen >= 32) false.B else true.B
+    def jr_res = !(x(12 ,2).orR)
+    def fsdsp = if (fLen >= 64) false.B else true.B
+    def fswsp32 = if (xLen == 64) false.B else if (fLen >= 32) false.B else true.B
+    Seq(false.B, fldsp, rd0, flwsp, jr_res, fsdsp, false.B, fswsp32)
+  }
+  def q3_ill = Seq.fill(8)(false.B)
+
+  def ill = {
+    val s = q0_ill ++ q1_ill ++ q2_ill ++ q3_ill
+    s(Cat(x(1,0), x(15,13)))
+  }
 }
 
 class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) extends Module with HasCoreParameters {
   val io = IO(new Bundle {
     val in = Input(UInt(32.W))
     val out = Output(new ExpandedInstruction)
     val rvc = Output(Bool())
+    val ill = Output(Bool())
   })
 
   if (usingCompressed) {
     io.rvc := io.in(1,0) =/= 3.U
-    io.out := new RVCDecoder(io.in, p(XLen), useAddiForMv).decode
+    val decoder = new RVCDecoder(io.in, p(XLen), fLen, useAddiForMv)
+    io.out := decoder.decode
+    io.ill := decoder.ill
   } else {
     io.rvc := false.B
-    io.out := new RVCDecoder(io.in, p(XLen), useAddiForMv).passthrough
+    io.out := new RVCDecoder(io.in, p(XLen), fLen, useAddiForMv).passthrough
+    io.ill := false.B // only used for RVC
   }
 }

src/main/scala/rocket/RocketCore.scala

@@ -830,15 +830,18 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   val tval_valid = wb_xcpt && (tval_any_addr || tval_inst)
   csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv)
   csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U)
-  csr.io.htval := {
+  val (htval, mhtinst_read_pseudo) = {
     val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U
     val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U)
     assert(!htval_valid_imem || io.imem.gpa.valid)
 
     val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR
     val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U)
 
-    (htval_dmem | htval_imem) >> hypervisorExtraAddrBits
+    val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits
+    // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation
+    val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem)
+    (htval, mhtinst_read_pseudo)
   }
 
   csr.io.vector.foreach { v =>
@@ -874,6 +877,8 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
     }
   }
 
+  csr.io.htval := htval
+  csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo
   io.ptw.ptbr := csr.io.ptbr
   io.ptw.hgatp := csr.io.hgatp
   io.ptw.vsatp := csr.io.vsatp