fix connection in VFU

chipsalliance · Jul 13, 2023 · af65b07 · af65b07
1 parent ce4da50
commit af65b07
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
@@ -7,6 +7,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.{DontCare, WireInit, withClock, withReset}
 import chisel3.experimental.SourceInfo
+import chisel3.experimental.dataview._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.rocket.Instructions._
@@ -767,7 +768,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
   val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
 
   val cp_ctrl = Wire(new FPUCtrlSigs)
-  cp_ctrl <> io.cp_req.bits
+  cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
   io.cp_resp.valid := false.B
   io.cp_resp.bits.data := 0.U
 
@@ -821,7 +822,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
   def fuInput(minT: Option[FType]): FPInput = {
     val req = Wire(new FPInput)
     val tag = ex_ctrl.typeTagIn
-    req := ex_ctrl
+    req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
     req.rm := ex_rm
     req.in1 := unbox(ex_rs(0), tag, minT)
     req.in2 := unbox(ex_rs(1), tag, minT)