Merge pull request #3475 from chipsalliance/fixes

Fixes for latest chisel

src/main/scala/amba/ahb/Xbar.scala

@@ -46,7 +46,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
 
       when (in.hready) { d_sel := a_sel }
       (a_sel zip io_out) foreach { case (sel, out) =>
-        out :<>= in
+        out.squeezeAll :<>= in.squeezeAll
         out.hsel := in.hsel && sel
         out.hmaster.map { _ := 0.U }
       }

src/main/scala/amba/apb/Xbar.scala

@@ -43,7 +43,7 @@ class APBFanout()(implicit p: Parameters) extends LazyModule {
 
       val sel = VecInit(route_addrs.map(seq => seq.map(_.contains(in.paddr)).reduce(_ || _)))
       (sel zip io_out) foreach { case (sel, out) =>
-        out :<>= in
+        out.squeezeAll :<>= in.squeezeAll
         out.psel    := sel && in.psel
         out.penable := sel && in.penable
       }

src/main/scala/amba/axi4/RegisterRouter.scala

@@ -48,8 +48,8 @@ case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes
     aw.ready := in.ready && !ar.valid && w .valid
     w .ready := in.ready && !ar.valid && aw.valid
 
-    ar_extra :<= ar.bits.echo
-    aw_extra :<= aw.bits.echo
+    ar_extra.waiveAll :<= ar.bits.echo
+    aw_extra.waiveAll :<= aw.bits.echo
     ar_extra(AXI4RRId) := ar.bits.id
     aw_extra(AXI4RRId) := aw.bits.id
     val addr = Mux(ar.valid, ar.bits.addr, aw.bits.addr)
@@ -75,11 +75,11 @@ case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes
     r.bits.data := out.bits.data
     r.bits.last := true.B
     r.bits.resp := AXI4Parameters.RESP_OKAY
-    r.bits.echo :<= out.bits.extra
+    r.bits.echo :<= out.bits.extra.waiveAll
 
     b.bits.id   := out.bits.extra(AXI4RRId)
     b.bits.resp := AXI4Parameters.RESP_OKAY
-    b.bits.echo :<= out.bits.extra
+    b.bits.echo :<= out.bits.extra.waiveAll
   }
 }
 

src/main/scala/amba/axi4/Xbar.scala

@@ -85,7 +85,7 @@ class AXI4Xbar(
     // Transform input bundles
     val in = Wire(Vec(io_in.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until in.size) {
-      in(i) :<>= io_in(i)
+      in(i).squeezeAll :<>= io_in(i).squeezeAll
 
       // Handle size = 1 gracefully (Chisel3 empty range is broken)
       def trim(id: UInt, size: Int) = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
@@ -168,7 +168,7 @@ class AXI4Xbar(
     // Transform output bundles
     val out = Wire(Vec(io_out.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until out.size) {
-      io_out(i) :<>= out(i)
+      io_out(i).squeezeAll :<>= out(i).squeezeAll
 
       if (io_in.size > 1) {
         // Block AW if we cannot record the W source

src/main/scala/groundtest/DummyPTW.scala

@@ -15,7 +15,7 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
   val io = IO(new Bundle {
     val requestors = Flipped(Vec(n, new TLBPTWIO))
   })
-
+  io.requestors := DontCare
   val req_arb = Module(new RRArbiter(Valid(new PTWReq), n))
   req_arb.io.in <> io.requestors.map(_.req)
   req_arb.io.out.ready := true.B

src/main/scala/groundtest/Tile.scala

@@ -45,6 +45,7 @@ abstract class GroundTestTile(
     InModuleBody {
       m.module match {
         case module: DCacheModule => module.tlb_port := DontCare
+        case other => other
       }
     }
   }
@@ -58,6 +59,7 @@ class GroundTestTileModuleImp(outer: GroundTestTile) extends BaseTileModuleImp(o
 
   outer.dcacheOpt foreach { dcache =>
     val ptw = Module(new DummyPTW(1))
+    ptw.io.requestors := DontCare
     ptw.io.requestors.head <> dcache.module.io.ptw
   }
 }

src/main/scala/rocket/HellaCache.scala

@@ -274,6 +274,7 @@ trait HasHellaCache { this: BaseTile =>
   InModuleBody {
     dcache.module match {
       case module: DCacheModule => module.tlb_port := DontCare
+      case other => other
     }
   }
 }

src/main/scala/rocket/ICache.scala

@@ -636,6 +636,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
       io.resp.bits.data := Mux1H(s1_tag_hit, s1_dout)
       io.resp.bits.ae := s1_tl_error.asUInt.orR
       io.resp.valid := s1_valid && s1_hit
+      io.resp.bits.replay := false.B
 
     // if I$ latency is 2, can have ITIM and ECC.
     case 2 =>

src/main/scala/rocket/NBDcache.scala

@@ -449,7 +449,9 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu
   val free_sdq = io.replay.fire && isWrite(io.replay.bits.cmd)
   io.replay.bits.data := sdq(RegEnable(replay_arb.io.out.bits.sdq_id, free_sdq))
   io.replay.bits.mask := 0.U
-  io.replay <> replay_arb.io.out
+  io.replay.valid := replay_arb.io.out.valid
+  replay_arb.io.out.ready := io.replay.ready
+  io.replay.bits.viewAsSupertype(new HellaCacheReqInternal) <> replay_arb.io.out.bits.viewAsSupertype(new HellaCacheReqInternal)
 
   when (io.replay.valid || sdq_enq) {
     sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) |
@@ -707,6 +709,9 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
   require(cacheParams.tagCode.isInstanceOf[IdentityCode])
   val dECC = cacheParams.dataCode
 
+  io.cpu := DontCare
+  io.errors := DontCare
+
   val wb = Module(new WritebackUnit)
   val prober = Module(new ProbeUnit)
   val mshrs = Module(new MSHRFile)

src/main/scala/tilelink/Broadcast.scala

@@ -367,6 +367,7 @@ class BroadcastFilter(params: ProbeFilterParams) extends ProbeFilter(params) {
   io.response.bits.needT   := io.request.bits.needT
   io.response.bits.allocOH := io.request.bits.allocOH
   io.response.bits.gaveT   := true.B
+  io.response.bits.cacheOH := DontCare
   if (params.caches > 0)
     io.response.bits.cacheOH := ~0.U(params.caches.W)
 

src/main/scala/tilelink/Fragmenter.scala

@@ -313,7 +313,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
         val fullMask = ((BigInt(1) << beatBytes) - 1).U
         assert (!repeater.io.full || in_a.bits.mask === fullMask)
         out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
-        out.a.bits.user :<= in.a.bits.user.subset(_.isData)
+        out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
 
         // Tie off unused channels
         in.b.valid := false.B

src/main/scala/util/BundleMap.scala

@@ -112,7 +112,7 @@ class BundleMap(val fields: Seq[BundleFieldBase]) extends Record {
   // Create a new BundleMap with only the selected Keys retained
   def subset(fn: BundleKeyBase => Boolean): BundleMap = {
     val out = Wire(BundleMap(fields.filter(x => fn(x.key))))
-    out :<= this
+    out :<= this.waiveAll
     out
   }
 }

src/main/scala/util/LatencyPipe.scala

@@ -19,7 +19,7 @@ class LatencyPipe[T <: Data](typ: T, latency: Int) extends Module {
 
 object LatencyPipe {
   def apply[T <: Data](in: DecoupledIO[T], latency: Int): DecoupledIO[T] = {
-    val pipe = Module(new LatencyPipe(in.bits, latency))
+    val pipe = Module(new LatencyPipe(chiselTypeOf(in.bits), latency))
     pipe.io.in <> in
     pipe.io.out
   }