Change the condition of mul/div illegal instruction trap

Signed-off-by: kanataso <[email protected]>
chipsalliance · Jul 17, 2023 · 7774cd0 · 7774cd0
1 parent a5b829a
commit 7774cd0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -328,7 +328,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   }
   val id_illegal_rnum = if (usingCryptoNIST) (id_ctrl.zkn && aluFn.isKs1(id_ctrl.alu_fn) && id_inst(0)(23,20) > 0xA.U(4.W)) else false.B
   val id_illegal_insn = !id_ctrl.legal ||
-    (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||
+    id_ctrl.div && !csr.io.status.isa('m'-'a') ||
     id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
     id_ctrl.fp && (csr.io.decode(0).fp_illegal || io.fpu.illegal_rm) ||
     id_ctrl.dp && !csr.io.status.isa('d'-'a') ||