Skip to content

Commit

Permalink
Merge pull request #3674 from libresilicon/litex2
Browse files Browse the repository at this point in the history 
Litex2
  • Loading branch information
@jerryz123
jerryz123 authored Aug 22, 2024
2 parents cff28b8 + 445b5da commit 50744b3
Show file tree
Hide file tree
Showing 6 changed files with 327 additions and 1 deletion.
64 changes: 63 additions & 1 deletion build.sc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -185,6 +185,35 @@ trait Emulator extends Cross.Module2[String, String] {
}
}

object litexgenerate extends Module {
def compile = T {
os.proc("firtool",
generator.chirrtl().path,
s"--annotation-file=${generator.chiselAnno().path}",
"--disable-annotation-unknown",
"-dedup",
"-O=debug",
"--split-verilog",
"--preserve-values=named",
"--output-annotation-file=mfc.anno.json",
"--lowering-options=disallowLocalVariables",
s"-o=${T.dest}"
).call(T.dest)
PathRef(T.dest)
}

def rtls = T {
os.read(compile().path / "filelist.f").split("\n").map(str =>
try {
os.Path(str)
} catch {
case e: IllegalArgumentException if e.getMessage.contains("is not an absolute path") =>
compile().path / str.stripPrefix("./")
}
).filter(p => p.ext == "v" || p.ext == "sv").map(PathRef(_)).toSeq
}
}

object mfccompiler extends Module {
def compile = T {
os.proc("firtool",
Expand Down Expand Up @@ -233,7 +262,7 @@ trait Emulator extends Cross.Module2[String, String] {
"debug_rob.cc",
"emulator.cc",
"remote_bitbang.cc",
).map(c => PathRef(csrcDir().path / c))
).map(c => PathRef(csrcDir().path / c))
}

def CMakeListsString = T {
Expand Down Expand Up @@ -347,6 +376,39 @@ object emulator extends Cross[Emulator](
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBConfig"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32BConfig"),

// Litex
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x1"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x2"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x4"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x8"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x1"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x2"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x4"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x8"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x1"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x2"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x4"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x8"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x1"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x2"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x4"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x8"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x1"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x2"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x4"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x8"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x1"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x2"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x4"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x8"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x1"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x2"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x4"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x8"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x1"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x2"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x4"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x8"),
)

object `runnable-riscv-test` extends mill.Cross[RiscvTest](
Expand Down
2 changes: 2 additions & 0 deletions src/main/scala/rocket/ALU.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -81,6 +81,8 @@ abstract class AbstractALU(implicit p: Parameters) extends CoreModule()(p) {
}

class ALU(implicit p: Parameters) extends AbstractALU()(p) {
override def desiredName = "RocketALU"

// ADD, SUB
val in2_inv = Mux(isSub(io.fn), ~io.in2, io.in2)
val in1_xor_in2 = io.in1 ^ in2_inv
Expand Down
Empty file removed src/main/scala/rocket/BitManipCrypto.scala
View file
Empty file.
Empty file removed src/main/scala/rocket/CryptoNIST.scala
View file
Empty file.
53 changes: 53 additions & 0 deletions src/main/scala/subsystem/Litex.scala
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,53 @@
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.

package freechips.rocketchip.subsystem

import chisel3.util._

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.devices.debug.{DebugModuleKey, DefaultDebugModuleParams, ExportDebug, JTAG, APB}
import freechips.rocketchip.devices.tilelink.{
BuiltInErrorDeviceParams, BootROMLocated, BootROMParams, CLINTKey, DevNullDevice, CLINTParams, PLICKey, PLICParams, DevNullParams
}
import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType}
import freechips.rocketchip.diplomacy.{
AddressSet, MonitorsEnabled,
}
import freechips.rocketchip.resources.{
DTSModel, DTSCompat, DTSTimebase, BigIntHexContext
}
import freechips.rocketchip.tile.{
MaxHartIdBits, RocketTileParams, BuildRoCC, AccumulatorExample, OpcodeSet, TranslatorExample, CharacterCountExample, BlackBoxExample
}
import freechips.rocketchip.util.ClockGateModelFile
import scala.reflect.ClassTag

class WithLitexMemPort extends Config((site, here, up) => {
case ExtMem => Some(MemoryPortParams(MasterPortParams(
base = x"8000_0000",
size = x"8000_0000",
beatBytes = site(MemoryBusKey).beatBytes,
idBits = 4), 1))
})

class WithLitexMMIOPort extends Config((site, here, up) => {
case ExtBus => Some(MasterPortParams(
base = x"1000_0000",
size = x"7000_0000",
beatBytes = site(SystemBusKey).beatBytes,
idBits = 4))
})

class WithLitexSlavePort extends Config((site, here, up) => {
case ExtIn => Some(SlavePortParams(
beatBytes = site(SystemBusKey).beatBytes,
idBits = 8,
sourceBits = 4))
})

class WithNBitMemoryBus(dataBits: Int) extends Config((site, here, up) => {
case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8)
})
209 changes: 209 additions & 0 deletions src/main/scala/system/Litex.scala
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,209 @@
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.

package freechips.rocketchip.system

import org.chipsalliance.cde.config.Config
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.{WithNBigCores, WithNMedCores, WithNSmallCores, WithRV32, WithFP16, WithHypervisor, With1TinyCore, WithScratchpadsOnly, WithCloneRocketTiles, WithB}

class BaseLitexConfig extends Config(
new WithLitexMemPort() ++
new WithLitexMMIOPort() ++
new WithLitexSlavePort ++
new WithNExtTopInterrupts(8) ++
new WithCoherentBusTopology ++
new BaseConfig
)

class LitexConfigSmall1x1 extends Config(
new WithNSmallCores(1) ++
new WithNBitMemoryBus(64) ++
new BaseLitexConfig
)

class LitexConfigSmall1x2 extends Config(
new WithNSmallCores(1) ++
new WithNBitMemoryBus(128) ++
new BaseLitexConfig
)

class LitexConfigSmall1x4 extends Config(
new WithNSmallCores(1) ++
new WithNBitMemoryBus(256) ++
new BaseLitexConfig
)

class LitexConfigSmall1x8 extends Config(
new WithNSmallCores(1) ++
new WithNBitMemoryBus(512) ++
new BaseLitexConfig
)

class LitexConfigSmall2x1 extends Config(
new WithNSmallCores(2) ++
new WithNBitMemoryBus(64) ++
new BaseLitexConfig
)

class LitexConfigSmall2x2 extends Config(
new WithNSmallCores(2) ++
new WithNBitMemoryBus(128) ++
new BaseLitexConfig
)

class LitexConfigSmall2x4 extends Config(
new WithNSmallCores(2) ++
new WithNBitMemoryBus(256) ++
new BaseLitexConfig
)

class LitexConfigSmall2x8 extends Config(
new WithNSmallCores(2) ++
new WithNBitMemoryBus(512) ++
new BaseLitexConfig
)

class LitexConfigSmall4x1 extends Config(
new WithNSmallCores(4) ++
new WithNBitMemoryBus(64) ++
new BaseLitexConfig
)

class LitexConfigSmall4x2 extends Config(
new WithNSmallCores(4) ++
new WithNBitMemoryBus(128) ++
new BaseLitexConfig
)

class LitexConfigSmall4x4 extends Config(
new WithNSmallCores(4) ++
new WithNBitMemoryBus(256) ++
new BaseLitexConfig
)

class LitexConfigSmall4x8 extends Config(
new WithNSmallCores(4) ++
new WithNBitMemoryBus(512) ++
new BaseLitexConfig
)

class LitexConfigSmall8x1 extends Config(
new WithNSmallCores(8) ++
new WithNBitMemoryBus(64) ++
new BaseLitexConfig
)

class LitexConfigSmall8x2 extends Config(
new WithNSmallCores(8) ++
new WithNBitMemoryBus(128) ++
new BaseLitexConfig
)

class LitexConfigSmall8x4 extends Config(
new WithNSmallCores(8) ++
new WithNBitMemoryBus(256) ++
new BaseLitexConfig
)

class LitexConfigSmall8x8 extends Config(
new WithNSmallCores(8) ++
new WithNBitMemoryBus(512) ++
new BaseLitexConfig
)

class LitexConfigBig1x1 extends Config(
new WithNBigCores(1) ++
new WithNBitMemoryBus(64) ++
new BaseLitexConfig
)

class LitexConfigBig1x2 extends Config(
new WithNBigCores(1) ++
new WithNBitMemoryBus(128) ++
new BaseLitexConfig
)

class LitexConfigBig1x4 extends Config(
new WithNBigCores(1) ++
new WithNBitMemoryBus(256) ++
new BaseLitexConfig
)

class LitexConfigBig1x8 extends Config(
new WithNBigCores(1) ++
new WithNBitMemoryBus(512) ++
new BaseLitexConfig
)

class LitexConfigBig2x1 extends Config(
new WithNBigCores(2) ++
new WithNBitMemoryBus(64) ++
new BaseLitexConfig
)

class LitexConfigBig2x2 extends Config(
new WithNBigCores(2) ++
new WithNBitMemoryBus(128) ++
new BaseLitexConfig
)

class LitexConfigBig2x4 extends Config(
new WithNBigCores(2) ++
new WithNBitMemoryBus(256) ++
new BaseLitexConfig
)

class LitexConfigBig2x8 extends Config(
new WithNBigCores(2) ++
new WithNBitMemoryBus(512) ++
new BaseLitexConfig
)

class LitexConfigBig4x1 extends Config(
new WithNBigCores(4) ++
new WithNBitMemoryBus(64) ++
new BaseLitexConfig
)

class LitexConfigBig4x2 extends Config(
new WithNBigCores(4) ++
new WithNBitMemoryBus(128) ++
new BaseLitexConfig
)

class LitexConfigBig4x4 extends Config(
new WithNBigCores(4) ++
new WithNBitMemoryBus(256) ++
new BaseLitexConfig
)

class LitexConfigBig4x8 extends Config(
new WithNBigCores(4) ++
new WithNBitMemoryBus(512) ++
new BaseLitexConfig
)

class LitexConfigBig8x1 extends Config(
new WithNBigCores(8) ++
new WithNBitMemoryBus(64) ++
new BaseLitexConfig
)

class LitexConfigBig8x2 extends Config(
new WithNBigCores(8) ++
new WithNBitMemoryBus(128) ++
new BaseLitexConfig
)

class LitexConfigBig8x4 extends Config(
new WithNBigCores(8) ++
new WithNBitMemoryBus(256) ++
new BaseLitexConfig
)

class LitexConfigBig8x8 extends Config(
new WithNBigCores(8) ++
new WithNBitMemoryBus(512) ++
new BaseLitexConfig
)

0 comments on commit 50744b3

Please sign in to comment.