More fixes to amba components

chipsalliance · Aug 20, 2023 · 13fe404 · 13fe404
1 parent 9aaac40
commit 13fe404
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Showing 4 changed files with 7 additions and 7 deletions.
diff --git a/src/main/scala/amba/ahb/Xbar.scala b/src/main/scala/amba/ahb/Xbar.scala
@@ -46,7 +46,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
 
       when (in.hready) { d_sel := a_sel }
       (a_sel zip io_out) foreach { case (sel, out) =>
-        out :<>= in
+        out.squeezeAll :<>= in.squeezeAll
         out.hsel := in.hsel && sel
         out.hmaster.map { _ := 0.U }
       }

diff --git a/src/main/scala/amba/apb/Xbar.scala b/src/main/scala/amba/apb/Xbar.scala
@@ -43,7 +43,7 @@ class APBFanout()(implicit p: Parameters) extends LazyModule {
 
       val sel = VecInit(route_addrs.map(seq => seq.map(_.contains(in.paddr)).reduce(_ || _)))
       (sel zip io_out) foreach { case (sel, out) =>
-        out :<>= in
+        out.squeezeAll :<>= in.squeezeAll
         out.psel    := sel && in.psel
         out.penable := sel && in.penable
       }

diff --git a/src/main/scala/amba/axi4/RegisterRouter.scala b/src/main/scala/amba/axi4/RegisterRouter.scala
@@ -48,8 +48,8 @@ case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes
     aw.ready := in.ready && !ar.valid && w .valid
     w .ready := in.ready && !ar.valid && aw.valid
 
-    ar_extra :<= ar.bits.echo
-    aw_extra :<= aw.bits.echo
+    ar_extra.waiveAll :<= ar.bits.echo
+    aw_extra.waiveAll :<= aw.bits.echo
     ar_extra(AXI4RRId) := ar.bits.id
     aw_extra(AXI4RRId) := aw.bits.id
     val addr = Mux(ar.valid, ar.bits.addr, aw.bits.addr)
@@ -75,11 +75,11 @@ case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes
     r.bits.data := out.bits.data
     r.bits.last := true.B
     r.bits.resp := AXI4Parameters.RESP_OKAY
-    r.bits.echo :<= out.bits.extra
+    r.bits.echo :<= out.bits.extra.waiveAll
 
     b.bits.id   := out.bits.extra(AXI4RRId)
     b.bits.resp := AXI4Parameters.RESP_OKAY
-    b.bits.echo :<= out.bits.extra
+    b.bits.echo :<= out.bits.extra.waiveAll
   }
 }
 

diff --git a/src/main/scala/amba/axi4/Xbar.scala b/src/main/scala/amba/axi4/Xbar.scala
@@ -168,7 +168,7 @@ class AXI4Xbar(
     // Transform output bundles
     val out = Wire(Vec(io_out.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until out.size) {
-      io_out(i) :<>= out(i)
+      io_out(i).squeezeAll :<>= out(i).squeezeAll
 
       if (io_in.size > 1) {
         // Block AW if we cannot record the W source