Zicond: implement czero.eqz, czero.nez

chipsalliance · Apr 23, 2023 · 0f259ca · 0f259ca
1 parent 0815dba
commit 0f259ca
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Showing 4 changed files with 16 additions and 1 deletion.
diff --git a/src/main/scala/rocket/ALU.scala b/src/main/scala/rocket/ALU.scala
@@ -19,6 +19,8 @@ class ALUFN {
   def FN_SR   = 5.U
   def FN_OR   = 6.U
   def FN_AND  = 7.U
+  def FN_CZEQZ = 8.U
+  def FN_CZNEZ = 9.U
   def FN_SUB  = 10.U
   def FN_SRA  = 11.U
   def FN_SLT  = 12.U
@@ -160,10 +162,19 @@ class ALU(implicit p: Parameters) extends AbstractALU(new ALUFN)(p) {
   val shout = Mux(io.fn === aluFn.FN_SR || io.fn === aluFn.FN_SRA, shout_r, 0.U) |
               Mux(io.fn === aluFn.FN_SL,                           shout_l, 0.U)
 
+  // CZEQZ, CZNEZ
+  val cond_out = Option.when(coreParams.useConditionalZero)(
+    Mux(io.fn === aluFn.FN_CZEQZ && io.in2 =/= 0.U, io.in1, 0.U) |
+    Mux(io.fn === aluFn.FN_CZNEZ && io.in2 === 0.U, io.in1, 0.U)
+  )
+
   // AND, OR, XOR
   val logic = Mux(io.fn === aluFn.FN_XOR || io.fn === aluFn.FN_OR, in1_xor_in2, 0.U) |
               Mux(io.fn === aluFn.FN_OR || io.fn === aluFn.FN_AND, io.in1 & io.in2, 0.U)
-  val shift_logic = (aluFn.isCmp(io.fn) && slt) | logic | shout
+  val shift_logic = cond_out match {
+    case Some(co) => (aluFn.isCmp (io.fn) && slt) | logic | shout | co
+    case _ => (aluFn.isCmp (io.fn) && slt) | logic | shout
+  }
   val out = Mux(io.fn === aluFn.FN_ADD || io.fn === aluFn.FN_SUB, io.adder_out, shift_logic)
 
   io.out := out

diff --git a/src/main/scala/rocket/IDecode.scala b/src/main/scala/rocket/IDecode.scala
@@ -111,6 +111,8 @@ class IDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends Decode
     SLL->       List(Y,N,N,N,N,N,Y,Y,N,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SL,    N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
     SRL->       List(Y,N,N,N,N,N,Y,Y,N,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SR,    N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
     SRA->       List(Y,N,N,N,N,N,Y,Y,N,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SRA,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
+    CZERO_EQZ-> List(Y,N,N,N,N,N,Y,Y,N,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_CZEQZ, N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
+    CZERO_NEZ-> List(Y,N,N,N,N,N,Y,Y,N,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_CZNEZ, N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
 
     FENCE->     List(Y,N,N,N,N,N,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  aluFn.FN_X,     N,M_X,        N,N,N,N,N,N,N,CSR.N,N,Y,N,N),
 

diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -29,6 +29,7 @@ case class RocketCoreParams(
   useBitManipCrypto: Boolean = false,
   useCryptoNIST: Boolean = false,
   useCryptoSM: Boolean = false,
+  useConditionalZero: Boolean = false,
   nLocalInterrupts: Int = 0,
   useNMI: Boolean = false,
   nBreakpoints: Int = 1,

diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala
@@ -29,6 +29,7 @@ trait CoreParams {
   val useCryptoNIST: Boolean
   val useCryptoSM: Boolean
   val useRVE: Boolean
+  val useConditionalZero: Boolean
   val mulDiv: Option[MulDivParams]
   val fpu: Option[FPUParams]
   val fetchWidth: Int