remove CompileOption in tilelink Broadcast

chipsalliance · Jul 27, 2023 · 07d1b57 · 07d1b57
1 parent 7c9670b
commit 07d1b57
Showing 1 changed file with 3 additions and 4 deletions.
diff --git a/src/main/scala/tilelink/Broadcast.scala b/src/main/scala/tilelink/Broadcast.scala
@@ -4,7 +4,6 @@ package freechips.rocketchip.tilelink
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
@@ -119,7 +118,7 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz
       val d_what = out.d.bits.source(d_high+1, d_high)
       val d_drop = d_what === DROP
       val d_hasData = edgeOut.hasData(out.d.bits)
-      val d_normal = Wire(in.d)
+      val d_normal = Wire(chiselTypeOf(in.d))
       val (d_first, d_last, _) = edgeIn.firstlast(d_normal)
       val d_trackerOH = VecInit(trackers.map { t => t.need_d && t.source === d_normal.bits.source }).asUInt holdUnless d_first
 
@@ -179,8 +178,8 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz
           in.c.bits.param === TLPermissions.BtoB)
       }
 
-      val releaseack = Wire(in.d)
-      val putfull = Wire(out.a)
+      val releaseack = Wire(chiselTypeOf(in.d))
+      val putfull = Wire(chiselTypeOf(out.a))
 
       in.c.ready := c_probeack || Mux(c_release, releaseack.ready, putfull.ready)