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arm: dts: xilinx: add zynq-zed-adv7511-ad7380.dts
Signed-off-by: David Lechner <[email protected]>
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// SPDX-License-Identifier: GPL-2.0 | ||
/* | ||
* Analog Devices EVAL-AD7983FMCZ | ||
* https://www.analog.com/en/products/ad7983.html | ||
* https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad7383.html | ||
* | ||
* hdl_project: <ad738x_fmc/zed> | ||
* board_revision: <?> | ||
* | ||
* Copyright (C) 2023 Analog Devices Inc. | ||
* Copyright (C) 2023 BayLibre, SAS | ||
*/ | ||
/dts-v1/; | ||
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#include <dt-bindings/dma/axi-dmac.h> | ||
#include <dt-bindings/gpio/gpio.h> | ||
#include <dt-bindings/interrupt-controller/irq.h> | ||
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#include "zynq-zed.dtsi" | ||
#include "zynq-zed-adv7511.dtsi" | ||
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/ { | ||
eval_u2: eval-board-u2-regulator { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "EVAL +3.3V supply (U2)"; | ||
regulator-min-microvolt = <3300000>; | ||
regulator-max-microvolt = <3300000>; | ||
regulator-always-on; | ||
}; | ||
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eval_u3: eval-board-u3-regulator { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "EVAL +3.3V supply (U3)"; | ||
regulator-min-microvolt = <3300000>; | ||
regulator-max-microvolt = <3300000>; | ||
regulator-always-on; | ||
}; | ||
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eval_u6: eval-board-u6-regulator { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "EVAL +2.3V supply (U6)"; | ||
regulator-min-microvolt = <2300000>; | ||
regulator-max-microvolt = <2300000>; | ||
regulator-always-on; | ||
}; | ||
}; | ||
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&fpga_axi { | ||
adc_trigger: pwm@44b00000 { | ||
compatible = "adi,axi-pwmgen"; | ||
reg = <0x44b00000 0x1000>; | ||
label = "adc_conversion_trigger"; | ||
#pwm-cells = <2>; | ||
clocks = <&spi_clk>; | ||
}; | ||
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rx_dma: rx-dmac@44a30000 { | ||
compatible = "adi,axi-dmac-1.00.a"; | ||
reg = <0x44a30000 0x1000>; | ||
#dma-cells = <1>; | ||
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&clkc 17>; | ||
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adi,channels { | ||
#size-cells = <0>; | ||
#address-cells = <1>; | ||
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dma-channel@0 { | ||
reg = <0>; | ||
adi,source-bus-width = <32>; | ||
adi,source-bus-type = <AXI_DMAC_BUS_TYPE_AXI_STREAM>; | ||
adi,destination-bus-width = <64>; | ||
adi,destination-bus-type = <AXI_DMAC_BUS_TYPE_AXI_MM>; | ||
}; | ||
}; | ||
}; | ||
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spi_clk: clock-controller@44a70000 { | ||
compatible = "adi,axi-clkgen-2.00.a"; | ||
reg = <0x44a70000 0x1000>; | ||
#clock-cells = <0>; | ||
clocks = <&clkc 15>; | ||
clock-names = "s_axi_aclk", "clkin1"; | ||
clock-output-names = "spi_clk"; | ||
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/* 2x required SCLK rate */ | ||
assigned-clocks = <&spi_clk>; | ||
assigned-clock-rates = <160000000>; | ||
}; | ||
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axi_spi_engine_0: spi@44a00000 { | ||
compatible = "adi,axi-spi-engine-1.00.a"; | ||
reg = <0x44a00000 0x1000>; | ||
interrupt-parent = <&intc>; | ||
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&clkc 15>, <&spi_clk>; | ||
clock-names = "s_axi_aclk", "spi_clk"; | ||
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#address-cells = <0x1>; | ||
#size-cells = <0x0>; | ||
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offloads { | ||
#address-cells = <0x1>; | ||
#size-cells = <0x0>; | ||
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offload_0: offload@0 { | ||
reg = <0>; | ||
compatible = "adi,axi-spi-engine-offload-pwm-trigger-dma-output"; | ||
pwms = <&adc_trigger 0 0>; | ||
dmas = <&rx_dma 0>; | ||
dma-names = "rx"; | ||
}; | ||
}; | ||
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ad7383: adc@0 { | ||
compatible = "adi,ad7383"; | ||
reg = <0>; | ||
spi-cpol; | ||
// TODO: awaiting HDL fix for CPHA | ||
// spi-cpha; | ||
spi-max-frequency = <80000000>; /* 12.5 ns period */ | ||
adi,sdo-mode = "1-wire"; | ||
vcc-supply = <&eval_u2>; | ||
vlogic-supply = <&eval_u6>; | ||
refio-supply = <&eval_u3>; | ||
adi,offloads = <&offload_0>; | ||
}; | ||
}; | ||
}; |