Updated CPM Example Design list

Xilinx · Nov 18, 2023 · e764afa · e764afa
1 parent 9a7b6c6
commit e764afa
Showing 1 changed file with 30 additions and 16 deletions.
diff --git a/...e/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst b/...e/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst
@@ -3,28 +3,42 @@
 Versal ACAP CPM Example Designs
 ===============================
 
-* Versal ACAP CPM5 QDMA Simulation Example Design
+* Versal Adaptive SoC CPM5 QDMA Simulation Example Design
     - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma
-* Versal ACAP CPM4 QDMA Simulation Example Design
+* Versal Adaptive SoC CPM4 QDMA Simulation Example Design
     - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma 
-* Veral ACAP CPM5 BMD Simulation Example Design
+* Versal Adaptive SoC CPM5 BMD Simulation Example Design
     - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd
-* Veral ACAP CPM4 BMD Simulation Example Design
+* Versal Adaptive SoC CPM4 BMD Simulation Example Design
     - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd
-* Versal ACAP CPM - Using PCIe Link for Debug
-    - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug
-* Veral ACAP Tandem PCIe Example Design
-    - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe
-* Versal ACAP CPM4/CPM5 AXI Bridge Root Complex Example Design
+* Versal Adaptive SoC CPM - Using PCIe Link for Debug
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug
+* Versal Adaptive SoC CPM Tandem PCIe Example Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe
+* Versal Adaptive SoC CPM4/CPM5 AXI Bridge Root Complex Example Design
     - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design
-* Versal ACAP CPM Gen4x8 QDMA Endpoint Example Design
-    - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_Gen4x8_QDMA_EP_Design
-* Versal ACAP CPM5 PCIE PIO Example Design 
+* Versal Adaptive SoC CPM4 QDMA Gen4x8 MM/ST Example Design 
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma 
+* Versal Adaptive SoC CPM4 QDMA Gen4x8 Performance Example Design 
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma_perf 
+* Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen4x8 MM/ST Example Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_dual_ctrl 
+* Versal Adaptive SoC CPM5 QDMA Gen5x8 MM Only Performance Example Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_g5x8_mm_perf 
+* Versal Adaptive SoC CPM5 QDMA Gen4x8 MM/ST Example Design 
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_mm_st 
+* Versal Adaptive SoC CPM5 QDMA Gen4x8 ST Only Performance Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_st_only 
+* Versal Adaptive SoC CPM5 PCIE PIO Example Design 
     - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio
-* Versal ACAP CPM4 PCIE PIO Example Design 
+* Versal Adaptive SoC CPM4 PCIE PIO Example Design 
     - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio
-* Versal ACAP CPM5 PCIE BMD EndPoint Example Design
+* Versal Adaptive SoC CPM5 PCIE BMD EndPoint Example Design
     - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep
-* Versal ACAP CPM4 PCIE BMD EndPoint Example Design
-    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep 
+* Versal Adaptive SoC CPM4 PCIE BMD EndPoint Example Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep
+* Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen5x8 Performance Example Design (Part Based)
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_dual_perf  
+* Versal Adaptive SoC CPM5 QDMA Gen5x8 ST Performance Example Design (Part Based)
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_st_perf