Update versal_acap_cpm_example_designs.rst

Xilinx · Nov 18, 2023 · 9a7b6c6 · 9a7b6c6
1 parent 943dd0c
commit 9a7b6c6
Showing 1 changed file with 16 additions and 8 deletions.
diff --git a/...e/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst b/...e/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst
@@ -4,19 +4,27 @@ Versal ACAP CPM Example Designs
 ===============================
 
 * Versal ACAP CPM5 QDMA Simulation Example Design
-    - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM5_QDMA_Simulation_Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma
+* Versal ACAP CPM4 QDMA Simulation Example Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma 
 * Veral ACAP CPM5 BMD Simulation Example Design
-    - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM5_PCIe_BMD_Simulation_Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd
+* Veral ACAP CPM4 BMD Simulation Example Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd
 * Versal ACAP CPM - Using PCIe Link for Debug
     - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug
 * Veral ACAP Tandem PCIe Example Design
     - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe
-* Versal ACAP CPM AXI Bridge Root Complex Example Design
-    - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_AXI_Bridge_RootPort_Design
+* Versal ACAP CPM4/CPM5 AXI Bridge Root Complex Example Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design
 * Versal ACAP CPM Gen4x8 QDMA Endpoint Example Design
     - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_Gen4x8_QDMA_EP_Design
-* Versal ACAP CPM PCIE PIO Example Design 
-    - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_PCIE_PIO_Design
-* Versal ACAP CPM PCIE BMD Example Design for VCK190
-    - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/VCK190_CPM_PCIE_BMD
+* Versal ACAP CPM5 PCIE PIO Example Design 
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio
+* Versal ACAP CPM4 PCIE PIO Example Design 
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio
+* Versal ACAP CPM5 PCIE BMD EndPoint Example Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep
+* Versal ACAP CPM4 PCIE BMD EndPoint Example Design
+    - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep