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...e/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst
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| Versal ACAP CPM Example Designs | ||
| Versal Adaptive SoC CPM Example Designs | ||
| =============================== | ||
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| * Versal Adaptive SoC CPM5 QDMA Simulation Example Design | ||
| * (1) Versal Adaptive SoC CPM5 QDMA Simulation Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma | ||
| * Versal Adaptive SoC CPM4 QDMA Simulation Example Design | ||
| * (2) Versal Adaptive SoC CPM4 QDMA Simulation Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma | ||
| * Versal Adaptive SoC CPM5 BMD Simulation Example Design | ||
| * (3) Versal Adaptive SoC CPM5 BMD Simulation Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd | ||
| * Versal Adaptive SoC CPM4 BMD Simulation Example Design | ||
| * (4) Versal Adaptive SoC CPM4 BMD Simulation Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd | ||
| * Versal Adaptive SoC CPM - Using PCIe Link for Debug | ||
| * (5) Versal Adaptive SoC CPM - Using PCIe Link for Debug | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug | ||
| * Versal Adaptive SoC CPM Tandem PCIe Example Design | ||
| * (6) Versal Adaptive SoC CPM Tandem PCIe Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe | ||
| * Versal Adaptive SoC CPM4/CPM5 AXI Bridge Root Complex Example Design | ||
| * (7) Versal Adaptive SoC CPM4/CPM5 AXI Bridge Root Complex Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design | ||
| * Versal Adaptive SoC CPM4 QDMA Gen4x8 MM/ST Example Design | ||
| * (8) Versal Adaptive SoC CPM4 QDMA Gen4x8 MM/ST Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma | ||
| * Versal Adaptive SoC CPM4 QDMA Gen4x8 Performance Example Design | ||
| * (9) Versal Adaptive SoC CPM4 QDMA Gen4x8 Performance Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma_perf | ||
| * Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen4x8 MM/ST Example Design | ||
| * (10) Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen4x8 MM/ST Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_dual_ctrl | ||
| * Versal Adaptive SoC CPM5 QDMA Gen5x8 MM Only Performance Example Design | ||
| * (11) Versal Adaptive SoC CPM5 QDMA Gen5x8 MM Only Performance Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_g5x8_mm_perf | ||
| * Versal Adaptive SoC CPM5 QDMA Gen4x8 MM/ST Example Design | ||
| * (12) Versal Adaptive SoC CPM5 QDMA Gen4x8 MM/ST Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_mm_st | ||
| * Versal Adaptive SoC CPM5 QDMA Gen4x8 ST Only Performance Design | ||
| * (13) Versal Adaptive SoC CPM5 QDMA Gen4x8 ST Only Performance Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_st_only | ||
| * Versal Adaptive SoC CPM5 PCIE PIO Example Design | ||
| * (14) Versal Adaptive SoC CPM5 PCIE PIO Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio | ||
| * Versal Adaptive SoC CPM4 PCIE PIO Example Design | ||
| * (15) Versal Adaptive SoC CPM4 PCIE PIO Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio | ||
| * Versal Adaptive SoC CPM5 PCIE BMD EndPoint Example Design | ||
| * (16) Versal Adaptive SoC CPM5 PCIE BMD EndPoint Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep | ||
| * Versal Adaptive SoC CPM4 PCIE BMD EndPoint Example Design | ||
| * (17) Versal Adaptive SoC CPM4 PCIE BMD EndPoint Example Design | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep | ||
| * Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen5x8 Performance Example Design (Part Based) | ||
| * (18) Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen5x8 Performance Example Design (Part Based) | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_dual_perf | ||
| * Versal Adaptive SoC CPM5 QDMA Gen5x8 ST Performance Example Design (Part Based) | ||
| * (19) Versal Adaptive SoC CPM5 QDMA Gen5x8 ST Performance Example Design (Part Based) | ||
| - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_st_perf | ||
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