Merge pull request verilog-to-routing#2686 from AlexandreSinger/featu…

…re-lut-size-logging

[LOGGING] Fixed LUT Sizing Issue

vpr/src/base/read_circuit.cpp

@@ -4,10 +4,8 @@
 #include "atom_netlist.h"
 #include "atom_netlist_utils.h"
 #include "echo_files.h"
-
 #include "vtr_assert.h"
 #include "vtr_log.h"
-#include "vtr_util.h"
 #include "vtr_path.h"
 #include "vtr_time.h"
 
@@ -145,34 +143,31 @@ static void process_circuit(AtomNetlist& netlist,
 }
 
 static void show_circuit_stats(const AtomNetlist& netlist) {
+    // Count the block statistics
     std::map<std::string, size_t> block_type_counts;
-
-    //Count the block statistics
+    std::map<std::string, size_t> lut_size_counts;
     for (auto blk_id : netlist.blocks()) {
+        // For each model, count the number of occurrences in the netlist.
         const t_model* blk_model = netlist.block_model(blk_id);
+        ++block_type_counts[blk_model->name];
+        // If this block is a LUT, also count the occurences of this size of LUT
+        // for more logging information.
         if (blk_model->name == std::string(MODEL_NAMES)) {
-            //LUT
-            size_t lut_size = 0;
+            // May have zero (no input LUT) or one input port
             auto in_ports = netlist.block_input_ports(blk_id);
-
-            //May have zero (no input LUT) or one input port
+            VTR_ASSERT(in_ports.size() <= 1 && "Expected number of input ports for LUT to be 0 or 1");
+            size_t lut_size = 0;
             if (in_ports.size() == 1) {
+                // Use the number of pins in the input port to determine the
+                // size of the LUT.
                 auto port_id = *in_ports.begin();
-
-                //Figure out the LUT size
-                lut_size = netlist.port_width(port_id);
-
-            } else {
-                VTR_ASSERT(in_ports.size() == 0);
+                lut_size = netlist.port_pins(port_id).size();
             }
-
-            ++block_type_counts[std::to_string(lut_size) + "-LUT"];
-        } else {
-            //Other types
-            ++block_type_counts[blk_model->name];
+            ++lut_size_counts[std::to_string(lut_size) + "-LUT"];
         }
     }
-    //Count the net statistics
+
+    // Count the net statistics
     std::map<std::string, double> net_stats;
     for (auto net_id : netlist.nets()) {
         double fanout = netlist.net_sinks(net_id).size();
@@ -189,21 +184,32 @@ static void show_circuit_stats(const AtomNetlist& netlist) {
     }
     net_stats["Avg Fanout"] /= netlist.nets().size();
 
-    //Determine the maximum length of a type name for nice formatting
+    // Determine the maximum length of a type name for nice formatting
     size_t max_block_type_len = 0;
     for (const auto& kv : block_type_counts) {
         max_block_type_len = std::max(max_block_type_len, kv.first.size());
     }
+    size_t max_lut_size_len = 0;
+    for (const auto& kv : lut_size_counts) {
+        max_lut_size_len = std::max(max_lut_size_len, kv.first.size());
+    }
     size_t max_net_type_len = 0;
     for (const auto& kv : net_stats) {
         max_net_type_len = std::max(max_net_type_len, kv.first.size());
     }
 
-    //Print the statistics
+    // Print the statistics
     VTR_LOG("Circuit Statistics:\n");
     VTR_LOG("  Blocks: %zu\n", netlist.blocks().size());
     for (const auto& kv : block_type_counts) {
         VTR_LOG("    %-*s: %7zu\n", max_block_type_len, kv.first.c_str(), kv.second);
+        // If this block is a LUT, print the different sizes of LUTs in the
+        // design.
+        if (kv.first == std::string(MODEL_NAMES)) {
+            for (const auto& lut_kv : lut_size_counts) {
+                VTR_LOG("        %-*s: %7zu\n", max_lut_size_len, lut_kv.first.c_str(), lut_kv.second);
+            }
+        }
     }
     VTR_LOG("  Nets  : %zu\n", netlist.nets().size());
     for (const auto& kv : net_stats) {

vtr_flow/parse/parse_config/vpr_chain.txt

@@ -1,7 +1,7 @@
 %include "vpr_standard.txt"
 
 num_le;vpr.out;\s*Total number of Logic Elements used\s*:\s*(\d+)
-num_luts;vpr.out;\s*6-LUT\s*:\s*(\d+)
+num_luts;vpr.out;\s*.names\s*:\s*(\d+)
 num_add_blocks;odin.out;The Total Number of Hard Block adders: (\d+)
 max_add_chain_length;odin.out;The Number of Hard Block adders in the Longest Chain: (\d+)
 num_sub_blocks;odin.out;The Total Number of Hard Block subs: (\d+)

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt

@@ -1,3 +1,3 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_le	  num_luts	  num_add_blocks	  max_add_chain_length	  num_sub_blocks	  max_sub_chain_length	 
- k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml	  mult_4x4.v	  common	  1.20	  vpr	  62.24 MiB	  	  -1	  -1	  0.07	  20964	  1	  0.00	  -1	  -1	  33108	  -1	  -1	  3	  9	  0	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  63732	  9	  8	  75	  70	  1	  35	  20	  5	  5	  25	  clb	  auto	  23.6 MiB	  0.53	  86	  62.2 MiB	  0.00	  0.00	  2.25119	  -23.8925	  -2.25119	  2.25119	  0.02	  4.1023e-05	  3.1539e-05	  0.00122774	  0.00111409	  34	  203	  14	  151211	  75605.7	  45067.1	  1802.68	  0.10	  0.0179246	  0.0149981	  167	  11	  115	  154	  5391	  2823	  2.41865	  2.41865	  -33.4427	  -2.41865	  0	  0	  54748.7	  2189.95	  0.00	  0.01	  0.00322286	  0.00301138	  14	  16	  -1	  -1	  -1	  -1	 
- k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml	  mult_9x9.v	  common	  3.61	  vpr	  63.33 MiB	  	  -1	  -1	  0.09	  21268	  1	  0.01	  -1	  -1	  33200	  -1	  -1	  9	  19	  0	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  64852	  19	  18	  308	  249	  1	  147	  46	  6	  6	  36	  clb	  auto	  25.1 MiB	  2.32	  488	  63.3 MiB	  0.03	  0.00	  3.72642	  -71.3132	  -3.72642	  3.72642	  0.03	  0.000152812	  0.000121271	  0.0114902	  0.00973617	  54	  1211	  26	  403230	  226817	  113905.	  3164.04	  0.46	  0.0908276	  0.0791763	  883	  22	  949	  1423	  57002	  21423	  5.96246	  5.96246	  -123.664	  -5.96246	  0	  0	  146644.	  4073.44	  0.01	  0.03	  0.0171281	  0.0157138	  63	  81	  -1	  -1	  -1	  -1	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_le	num_luts	num_add_blocks	max_add_chain_length	num_sub_blocks	max_sub_chain_length	
+k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml	mult_4x4.v	common	3.59	vpr	61.01 MiB		-1	-1	0.11	16896	1	0.63	-1	-1	29740	-1	-1	3	9	0	-1	success	v8.0.0-10974-gd2d425477	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-08-16T01:29:20	betzgrp-wintermute.eecg.utoronto.ca	/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks	62476	9	8	75	70	1	37	20	5	5	25	clb	auto	22.4 MiB	0.47	82	533	165	363	5	61.0 MiB	0.01	0.00	2.68643	-29.137	-2.68643	2.68643	0.02	0.000188348	0.000174205	0.00474572	0.0044363	26	182	18	151211	75605.7	37105.9	1484.24	0.15	0.0423228	0.0352957	1908	5841	-1	155	11	111	124	5133	2870	2.88739	2.88739	-34.0156	-2.88739	0	0	45067.1	1802.68	0.00	0.01	0.01	-1	-1	0.00	0.00698364	0.00619778	14	18	-1	-1	-1	-1	
+k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml	mult_9x9.v	common	6.04	vpr	62.27 MiB		-1	-1	0.19	17208	1	0.64	-1	-1	30124	-1	-1	9	19	0	-1	success	v8.0.0-10974-gd2d425477	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-08-16T01:29:20	betzgrp-wintermute.eecg.utoronto.ca	/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks	63760	19	18	308	249	1	147	46	6	6	36	clb	auto	23.8 MiB	2.01	502	2916	768	2087	61	62.3 MiB	0.05	0.00	4.80297	-98.0082	-4.80297	4.80297	0.05	0.000629548	0.000584294	0.0259583	0.0242455	48	1077	40	403230	226817	104013.	2889.24	0.79	0.275306	0.234615	3910	18599	-1	770	17	746	1059	42320	17076	4.66916	4.66916	-105.494	-4.66916	0	0	131137.	3642.71	0.01	0.04	0.02	-1	-1	0.01	0.026422	0.0235947	63	83	-1	-1	-1	-1