Merge branch 'master' into dev

README.md

@@ -72,7 +72,7 @@ This repository hosts a RISC-V implementation written in SpinalHDL. Here are som
 - Linux compatible (SoC : https://github.com/enjoy-digital/linux-on-litex-vexriscv)
 - Zephyr compatible
 - [FreeRTOS port](https://github.com/Dolu1990/FreeRTOS-RISCV)
-- Support tightly coupled memory on I$ D$ (see GenFullWithTcm)
+- Support tightly coupled memory on I$ D$ (see GenFullWithTcm / GenFullWithTcmIntegrated)
 
 The hardware description of this CPU is done by using a very software oriented approach
 (without any overhead in the generated hardware). Here is a list of software concepts used:

build.sbt

@@ -1,4 +1,4 @@
-val spinalVersion = "dev"
+val spinalVersion = "1.9.4"
 
 lazy val root = (project in file(".")).
   settings(
@@ -7,17 +7,14 @@ lazy val root = (project in file(".")).
       scalaVersion := "2.11.12",
       version      := "2.0.0"
     )),
-    scalacOptions +=  s"-Xplugin:${new File(baseDirectory.value + s"/../SpinalHDL/idslplugin/target/scala-2.11/spinalhdl-idsl-plugin_2.11-$spinalVersion.jar")}",
-    scalacOptions += s"-Xplugin-require:idsl-plugin",
     libraryDependencies ++= Seq(
+      "com.github.spinalhdl" % "spinalhdl-core_2.11" % spinalVersion,
+      "com.github.spinalhdl" % "spinalhdl-lib_2.11" % spinalVersion,
+      compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % spinalVersion),
       "org.scalatest" %% "scalatest" % "3.2.5",
       "org.yaml" % "snakeyaml" % "1.8"
     ),
     name := "VexRiscv"
-  ).dependsOn(spinalHdlIdslPlugin, spinalHdlSim,spinalHdlCore,spinalHdlLib)
-lazy val spinalHdlIdslPlugin = ProjectRef(file("../SpinalHDL"), "idslplugin")
-lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "sim")
-lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "core")
-lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "lib")
+  )
 
 fork := true

doc/nativeJtag/README.md

@@ -49,7 +49,7 @@ as given could move with future changes to the file:
 ```
 [254]	val jtagCtrl = JtagTapInstructionCtrl()
 [255]	val tap = jtagCtrl.fromXilinxBscane2(userId = 2)
-[256]	jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK))
+[256]	jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK),0)
 ```
 Changing the above lines, removes the Murax SoC’s JTAG ports as pins of the FPGA and inserts the BSCANE2 Xilinx
 Debug IP to which the JTAG signals are now connected.
@@ -84,7 +84,7 @@ in e.g. the path:	`project_name.srcs\sources_1\imports\Downloads`
 [44]	wire tesic_tdo;
 [45]	reg  soc_tck,soc_tms,soc_tdi;
 [46]	wire soc_tdo;
-[47]	
+[47]
 [48]	always @(*) begin
 [49]		{soc_tck,  soc_tms,  soc_tdi  } = {tck,tms,tdi};
 [50]		tdo = soc_tdo;

src/main/scala/vexriscv/demo/GenFullWithTcmIntegrated.scala

@@ -0,0 +1,97 @@
+package vexriscv.demo
+
+import spinal.core._
+import spinal.lib.bus.misc.SizeMapping
+import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import vexriscv.plugin._
+import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
+
+/**
+ * this example integrate the tightly coupled memory directly inside VexRiscv
+ * by using the IBusDBusCachedTightlyCoupledRam plugin
+ */
+object GenFullWithTcmIntegrated extends App{
+  def config = VexRiscvConfig(
+    plugins = List(
+      new IBusDBusCachedTightlyCoupledRam(
+        mapping = SizeMapping(0x20000000, 0x1000)
+      ),
+      new IBusCachedPlugin(
+        prediction = DYNAMIC,
+        config = InstructionCacheConfig(
+          cacheSize = 4096,
+          bytePerLine =32,
+          wayCount = 1,
+          addressWidth = 32,
+          cpuDataWidth = 32,
+          memDataWidth = 32,
+          catchIllegalAccess = true,
+          catchAccessFault = true,
+          asyncTagMemory = false,
+          twoCycleRam = true,
+          twoCycleCache = true
+        ),
+        memoryTranslatorPortConfig = MmuPortConfig(
+          portTlbSize = 4
+        )
+      ),
+      new DBusCachedPlugin(
+        config = new DataCacheConfig(
+          cacheSize         = 4096,
+          bytePerLine       = 32,
+          wayCount          = 1,
+          addressWidth      = 32,
+          cpuDataWidth      = 32,
+          memDataWidth      = 32,
+          catchAccessError  = true,
+          catchIllegal      = true,
+          catchUnaligned    = true
+        ),
+        memoryTranslatorPortConfig = MmuPortConfig(
+          portTlbSize = 6
+        )
+      ),
+      new MmuPlugin(
+        virtualRange = _(31 downto 28) === 0xC,
+        ioRange      = _(31 downto 28) === 0xF
+      ),
+      new DecoderSimplePlugin(
+        catchIllegalInstruction = true
+      ),
+      new RegFilePlugin(
+        regFileReadyKind = plugin.SYNC,
+        zeroBoot = false
+      ),
+      new IntAluPlugin,
+      new SrcPlugin(
+        separatedAddSub = false,
+        executeInsertion = true
+      ),
+      new FullBarrelShifterPlugin,
+      new HazardSimplePlugin(
+        bypassExecute           = true,
+        bypassMemory            = true,
+        bypassWriteBack         = true,
+        bypassWriteBackBuffer   = true,
+        pessimisticUseSrc       = false,
+        pessimisticWriteRegFile = false,
+        pessimisticAddressMatch = false
+      ),
+      new MulPlugin,
+      new DivPlugin,
+      new CsrPlugin(CsrPluginConfig.small(0x80000020l)),
+      new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
+      new BranchPlugin(
+        earlyBranch = false,
+        catchAddressMisaligned = true
+      ),
+      new YamlPlugin("cpu0.yaml")
+    )
+  )
+
+  def cpu() = new VexRiscv(
+    config
+  )
+
+  SpinalVerilog(cpu())
+}

src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala

@@ -168,7 +168,7 @@ object VexRiscvAhbLite3{
 //            // On Artix FPGA jtag :
 //            val jtagCtrl = JtagTapInstructionCtrl()
 //            val tap = jtagCtrl.fromXilinxBscane2(userId = 1)
-//            jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK))
+//            jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK),0)
           }
           case _ =>
         }