IBusDBusCachedTightlyCoupledRam add missing write mask

SpinalHDL · Nov 2, 2023 · 0f17b39 · 0f17b39
1 parent 281818a
commit 0f17b39
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -680,7 +680,8 @@ class IBusDBusCachedTightlyCoupledRam(mapping : SizeMapping, withIBus : Boolean
           address = (dbus.address >> 2).resized,
           data    = dbus.write_data,
           enable  = dbus.enable,
-          write   = dbus.write_enable
+          write   = dbus.write_enable,
+          mask    = dbus.write_mask
         )
       }
       val i = withIBus generate new Area {