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Functionality corrections
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@tomtrafford
tomtrafford committed Aug 8, 2024
1 parent 5e765eb commit 382c4f8
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Showing 5 changed files with 85 additions and 75 deletions.
6 changes: 3 additions & 3 deletions modules/absenc/absenc.block.ini
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Original file line number Diff line number Diff line change
Expand Up @@ -13,9 +13,9 @@ description: Type of absolute/incremental protocol
1: BISS
2: enDat

[ENABLE]
type: bit_mux
description: Halt on falling edge, reset and enable on rising
[ENABLED]
type: read bit
description: Is ABSENC enabled?

[ENCODING]
type: param enum
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11 changes: 11 additions & 0 deletions modules/incenc/incenc.block.ini
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,17 @@ description: Signal detected
type: read bit
description: Quadrature homed status

[QPERIOD]
type: param time
description: Quadrature prescaler

[QSTATE]
type: read enum
description: Quadrature state
0: Disabled
1: At position
2: Slewing

[HEALTH]
type: read enum
description: Table status
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11 changes: 0 additions & 11 deletions modules/pmacenc/pmacenc.block.ini
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Original file line number Diff line number Diff line change
Expand Up @@ -38,17 +38,6 @@ description: Position encoding (for absolute encoders)
type: param uint 32
description: Number of bits

[QPERIOD]
type: param time
description: Quadrature prescaler

[QSTATE]
type: read enum
description: Quadrature state
0: Disabled
1: At position
2: Slewing

[CLK]
type: bit_out
description: Clock input from encoder
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119 changes: 64 additions & 55 deletions targets/PandABrick/hdl/PandABrick_encoders.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,7 @@ port (
ABSENC_STATUS_o : out std_logic_vector(31 downto 0);
ABSENC_HEALTH_o : out std_logic_vector(31 downto 0);
ABSENC_HOMED_o : out std_logic_vector(31 downto 0);
ABSENC_ENABLED_o : out std_logic_vector(31 downto 0);

UVWT_o : out std_logic;

Expand All @@ -107,7 +108,7 @@ signal bdat : std_logic;
signal Passthrough : std_logic;
signal UVWT : std_logic;
signal health_biss_slave : std_logic_vector(31 downto 0);
signal absenc_enable : std_logic;
-- signal absenc_enable : std_logic;

signal clk_out_encoder_ssi : std_logic;
signal clk_out_encoder_biss : std_logic;
Expand All @@ -122,6 +123,8 @@ signal posn_prev : std_logic_vector(31 downto 0);
signal bits_not_used : unsigned(4 downto 0);
signal inc_bits_not_used : unsigned(4 downto 0);

signal step, dir : std_logic;

signal homed_qdec : std_logic_vector(31 downto 0);
signal linkup_incr : std_logic;
signal linkup_incr_std32 : std_logic_vector(31 downto 0);
Expand Down Expand Up @@ -229,45 +232,51 @@ port map (
linkup_incr <= not DCARD_MODE_i(0);
linkup_incr_std32 <= x"0000000"&"000"&linkup_incr;

-- --
-- -- INCREMENTAL OUT
-- --
-- qenc_inst : entity work.qenc
-- port map (
-- clk_i => clk_i,
-- reset_i => reset_i,
-- QPERIOD => QPERIOD_i,
-- QPERIOD_WSTB => QPERIOD_WSTB_i,
-- QSTATE => QSTATE_o,
-- enable_i => enable_i,
-- posn_i => posn_i,
-- a_o => quad_a,
-- b_o => quad_b
-- );
--
-- INCREMENTAL OUT
--
qenc_inst : entity work.qenc
port map (
clk_i => clk_i,
reset_i => reset_i,
QPERIOD => QPERIOD_i,
QPERIOD_WSTB => QPERIOD_WSTB_i,
QSTATE => QSTATE_o,
enable_i => enable_i,
posn_i => posn_i,
a_o => quad_a,
b_o => quad_b,
step_o => step,
dir_o => dir
);

-----------------------------ABSENC---------------------------------------------

abs_ps_select: process(clk_i)
begin
if rising_edge(clk_i) then
-- BITS not begin used
bits_not_used <= 31 - (unsigned(ABSENC_BITS_i(4 downto 0))-1);
lp_test: for i in 31 downto 0 loop
-- Discard bits not being used and MSB and LSB and extend the sign.
-- Note that we need the loop to manipulate the vector. Slicing with \
-- variable indices is not synthesisable.
if (i > 31 - bits_not_used - unsigned(ABSENC_MSB_DISCARD_i) - unsigned(ABSENC_LSB_DISCARD_i)) then
if ((ABSENC_ENCODING_i=c_UNSIGNED_BINARY_ENCODING) or (ABSENC_ENCODING_i=c_UNSIGNED_GRAY_ENCODING)) then
abs_posn_o(i) <= '0';
else
-- sign extension
abs_posn_o(i) <= posn(31 - to_integer(bits_not_used + unsigned(MSB_DISCARD_i)));
end if;
-- Add the LSB_DISCARD on to posn index count and start there
else
abs_posn_o(i) <= posn(i + to_integer(unsigned(ABSENC_LSB_DISCARD_i)));
end if;
end loop lp_test;
if (ABSENC_ENABLED_o = TO_SVECTOR(1,32)) then
-- BITS not begin used
bits_not_used <= 31 - (unsigned(ABSENC_BITS_i(4 downto 0))-1);
lp_test: for i in 31 downto 0 loop
-- Discard bits not being used and MSB and LSB and extend the sign.
-- Note that we need the loop to manipulate the vector. Slicing with \
-- variable indices is not synthesisable.
if (i > 31 - bits_not_used - unsigned(ABSENC_MSB_DISCARD_i) - unsigned(ABSENC_LSB_DISCARD_i)) then
if ((ABSENC_ENCODING_i=c_UNSIGNED_BINARY_ENCODING) or (ABSENC_ENCODING_i=c_UNSIGNED_GRAY_ENCODING)) then
abs_posn_o(i) <= '0';
else
-- sign extension
abs_posn_o(i) <= posn(31 - to_integer(bits_not_used + unsigned(MSB_DISCARD_i)));
end if;
-- Add the LSB_DISCARD on to posn index count and start there
else
abs_posn_o(i) <= posn(i + to_integer(unsigned(ABSENC_LSB_DISCARD_i)));
end if;
end loop lp_test;
else
abs_posn_o <= (others => '0');
end if;
end if;
end process abs_ps_select;

Expand All @@ -279,24 +288,24 @@ end process abs_ps_select;
process(clk_i)
begin
if rising_edge(clk_i) then
case (INCENC_PROTOCOL_i) is
case (ABSENC_PROTOCOL_i) is
when "000" => -- SSI
if (DCARD_MODE_i(3 downto 1) = DCARD_MONITOR) then
posn <= posn_ssi_sniffer;
ABSENC_STATUS_o(0) <= linkup_ssi;
if (linkup_ssi = '0') then
ABSENC_HEALTH_o <= TO_SVECTOR(2,32);
else
ABSENC_HEALTH_o <= (others => '0');
-- if (DCARD_MODE_i(3 downto 1) = DCARD_MONITOR) then
posn <= posn_ssi_sniffer;
ABSENC_STATUS_o(0) <= linkup_ssi;
if (linkup_ssi = '0') then
ABSENC_HEALTH_o <= TO_SVECTOR(2,32);
else
ABSENC_HEALTH_o <= (others => '0');
end if;
else -- DCARD_CONTROL
posn <= posn_ssi;
ABSENC_STATUS_o <= (others => '0');
ABSENC_HEALTH_o <= (others=>'0');
end if;
-- else -- DCARD_CONTROL
-- posn <= posn_ssi;
-- ABSENC_STATUS_o <= (others => '0');
-- ABSENC_HEALTH_o <= (others=>'0');
-- end if;
ABSENC_HOMED_o <= TO_SVECTOR(1,32);

when "010" => -- BISS & Loopback
when "001" => -- BISS & Loopback
if (DCARD_MODE_i(3 downto 1) = DCARD_MONITOR) then
posn <= posn_biss_sniffer;
ABSENC_STATUS_o(0) <= linkup_biss_sniffer;
Expand Down Expand Up @@ -444,42 +453,42 @@ begin
case (PMACENC_PROTOCOL_i) is
when "000" => -- Passthrough - UVWT
PMACENC_HEALTH_o <= (others=>'0');
ABSENC_ENABLE <= '0';
ABSENC_ENABLED_o <= TO_SVECTOR(0,32);
UVWT <= '1';
Passthrough <= '1';
when "001" => -- Passthrough - Absolute
PMACENC_HEALTH_o <= (others=>'0');
ABSENC_ENABLE <= '1';
ABSENC_ENABLED_o <= TO_SVECTOR(1,32);
UVWT <= '0';
Passthrough <= '1';

when "010" => -- Read - Step/Direction
PMACENC_HEALTH_o <= (others=>'0');
ABSENC_ENABLE <= '1';
ABSENC_ENABLED_o <= TO_SVECTOR(1,32);
UVWT <= '0';
Passthrough <= '0';

when "011" => -- Generate - SSI
PMACENC_HEALTH_o <= (others=>'0');
ABSENC_ENABLE <= '1';
ABSENC_ENABLED_o <= TO_SVECTOR(1,32);
UVWT <= '0';
Passthrough <= '0';

when "100" => -- Generate - enDat
PMACENC_HEALTH_o <= std_logic_vector(to_unsigned(2,32)); --ENDAT not implemented
ABSENC_ENABLE <= '1';
ABSENC_ENABLED_o <= TO_SVECTOR(1,32);
UVWT <= '0';
Passthrough <= '0';

when "101" => -- Generate Biss
PMACENC_HEALTH_o <= health_biss_slave;
ABSENC_ENABLE <= '1';
ABSENC_ENABLED_o <= TO_SVECTOR(1,32);
UVWT <= '0';
Passthrough <= '0';

when others =>
PMACENC_HEALTH_o <= (others=>'0');
ABSENC_ENABLE <= '1';
ABSENC_ENABLED_o <= TO_SVECTOR(1,32);
UVWT <= '0';
Passthrough <= '0';

Expand Down
13 changes: 7 additions & 6 deletions targets/PandABrick/hdl/PandABrick_encoders_block.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -111,7 +111,6 @@ signal PMACENC_HEALTH : std_logic_vector(31 downto 0);
signal a_ext, b_ext, z_ext, data_ext : std_logic;
signal posn : std_logic_vector(31 downto 0);
signal enable : std_logic;
signal absenc_enable : std_logic;

signal clk_ext : std_logic;
-- Block Configuration Registers
Expand Down Expand Up @@ -145,6 +144,7 @@ signal ABSENC_MSB_DISCARD : std_logic_vector(31 downto 0);
signal INCENC_HEALTH : std_logic_vector(31 downto 0);
signal ABSENC_HEALTH : std_logic_vector(31 downto 0);
signal HOMED : std_logic_vector(31 downto 0);
signal ABSENC_ENABLED : std_logic_vector(31 downto 0);
signal ABSENC_HOMED : std_logic_vector(31 downto 0);

signal read_addr : natural range 0 to (2**read_address_i'length - 1);
Expand Down Expand Up @@ -206,9 +206,7 @@ port map (
DCARD_TYPE => DCARD_TYPE,
BITS => PMACENC_BITS,
BITS_WSTB => PMACENC_BITS_WSTB,
HEALTH => PMACENC_HEALTH,
QPERIOD => QPERIOD,
QSTATE => QSTATE
HEALTH => PMACENC_HEALTH
);

incenc_ctrl : entity work.incenc_ctrl
Expand Down Expand Up @@ -241,7 +239,9 @@ port map (
RST_ON_Z => RST_ON_Z,
RST_ON_Z_WSTB => open,
HEALTH => INCENC_HEALTH,
HOMED => HOMED
HOMED => HOMED,
QPERIOD => QPERIOD,
QSTATE => QSTATE
);

absenc_ctrl : entity work.absenc_ctrl
Expand All @@ -251,7 +251,6 @@ port map (
bit_bus_i => bit_bus_i,
pos_bus_i => pos_bus_i,
clk_from_bus => clk_ext,
enable_from_bus => absenc_enable, -- TO BE CONNECTED THROUGH TO ENCODERS.VHD

read_strobe_i => ABSENC_read_strobe_i,
read_address_i => read_address_i,
Expand Down Expand Up @@ -281,6 +280,7 @@ port map (
MSB_DISCARD_WSTB => open,
HEALTH => ABSENC_HEALTH,
HOMED => ABSENC_HOMED,
ENABLED => ABSENC_ENABLED, -- TO BE CONNECTED THROUGH TO ENCODERS.VHD
DCARD_TYPE => DCARD_TYPE
);

Expand Down Expand Up @@ -363,6 +363,7 @@ port map(
ABSENC_MSB_DISCARD_i => ABSENC_MSB_DISCARD(4 downto 0),
ABSENC_STATUS_o => ABSENC_STATUS,
ABSENC_HEALTH_o => ABSENC_HEALTH,
ABSENC_ENABLED_o => ABSENC_ENABLED,
ABSENC_HOMED_o => ABSENC_HOMED,

UVWT_o => UVWT_o,
Expand Down

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