Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Miscellaneous fixes and improvements for RISC-V #7043

Merged
merged 3 commits into from
Sep 25, 2024
Merged

Miscellaneous fixes and improvements for RISC-V #7043

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
a704a1d
core: riscv: Set exception return PC into XEPC for entering user mode
gagachang Sep 9, 2024
dc1b968
core: riscv: Fix misconfiguration of XSCRATCH when XRET to kernel mode
gagachang Sep 11, 2024
d36769d
core: riscv: Use sp as base register of load instructions
gagachang Sep 13, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion core/arch/riscv/kernel/thread_arch.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -502,7 +502,7 @@ static void set_ctx_regs(struct thread_ctx_regs *regs, unsigned long a0,
.a3 = a3,
.s0 = 0,
.sp = user_sp,
.ra = entry_func,
.epc = entry_func,
.status = status,
.ie = ie,
};
Expand Down
64 changes: 36 additions & 28 deletions core/arch/riscv/kernel/thread_rv.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -154,8 +154,8 @@ native_interrupt_from_kernel:
/* Restore XSTATUS */
load_xregs sp, THREAD_CTX_REG_STATUS, REG_T0
csrw CSR_XSTATUS, t0
/* Set scratch as thread_core_local */
csrw CSR_XSCRATCH, tp
/* We are going to XRET to kernel mode. Set XSCRATCH as 0 */
csrw CSR_XSCRATCH, 0
/* Restore all GPRs */
load_xregs sp, THREAD_CTX_REG_RA, REG_RA
load_xregs sp, THREAD_CTX_REG_GP, REG_GP
Expand Down Expand Up @@ -252,8 +252,8 @@ set_sp:
/* Restore XSTATUS */
load_xregs sp, THREAD_ABT_REG_STATUS, REG_T0
csrw CSR_XSTATUS, t0
/* Set scratch as thread_core_local */
csrw CSR_XSCRATCH, tp
/* We are going to XRET to kernel mode. Set XSCRATCH as 0 */
csrw CSR_XSCRATCH, 0

/* Update core local flags */
lw a0, THREAD_CORE_LOCAL_FLAGS(tp)
Expand Down Expand Up @@ -705,24 +705,28 @@ FUNC __thread_enter_user_mode , :
*/
csrw CSR_XSCRATCH, tp

/* Move struct thread_ctx_regs *regs to sp to reduce code size */
mv sp, a0

/* Set exception return PC */
load_xregs sp, THREAD_CTX_REG_EPC, REG_S0
csrw CSR_XEPC, s0
/* Set user ie */
load_xregs a0, THREAD_CTX_REG_IE, REG_S0
load_xregs sp, THREAD_CTX_REG_IE, REG_S0
csrw CSR_XIE, s0

/* Set user status */
load_xregs a0, THREAD_CTX_REG_STATUS, REG_S0
load_xregs sp, THREAD_CTX_REG_STATUS, REG_S0
csrw CSR_XSTATUS, s0

/* Load the rest of the general purpose registers */
load_xregs a0, THREAD_CTX_REG_RA, REG_RA, REG_TP
load_xregs a0, THREAD_CTX_REG_T0, REG_T0, REG_T2
load_xregs a0, THREAD_CTX_REG_S0, REG_S0, REG_S1
load_xregs a0, THREAD_CTX_REG_S2, REG_S2, REG_S11
load_xregs a0, THREAD_CTX_REG_T3, REG_T3, REG_T6
load_xregs a0, THREAD_CTX_REG_A0, REG_A0, REG_A7

/* Set exception program counter */
csrw CSR_XEPC, ra
load_xregs sp, THREAD_CTX_REG_RA, REG_RA
load_xregs sp, THREAD_CTX_REG_GP, REG_GP
load_xregs sp, THREAD_CTX_REG_TP, REG_TP
load_xregs sp, THREAD_CTX_REG_T0, REG_T0, REG_T2
load_xregs sp, THREAD_CTX_REG_S0, REG_S0, REG_S1
load_xregs sp, THREAD_CTX_REG_A0, REG_A0, REG_A7
load_xregs sp, THREAD_CTX_REG_S2, REG_S2, REG_S11
load_xregs sp, THREAD_CTX_REG_T3, REG_T3, REG_T6
load_xregs sp, THREAD_CTX_REG_SP, REG_SP /* sp must be last one */

/* Jump into user mode */
XRET
Expand All @@ -733,16 +737,17 @@ FUNC thread_resume , :
/* Disable global interrupts first */
csrc CSR_XSTATUS, CSR_XSTATUS_IE

/* Move struct thread_ctx_regs *regs to sp to reduce code size */
mv sp, a0

/* Restore epc */
load_xregs a0, THREAD_CTX_REG_EPC, REG_T0
load_xregs sp, THREAD_CTX_REG_EPC, REG_T0
csrw CSR_XEPC, t0

/* Restore ie */
load_xregs a0, THREAD_CTX_REG_IE, REG_T0
load_xregs sp, THREAD_CTX_REG_IE, REG_T0
csrw CSR_XIE, t0

/* Restore status */
load_xregs a0, THREAD_CTX_REG_STATUS, REG_T0
load_xregs sp, THREAD_CTX_REG_STATUS, REG_T0
csrw CSR_XSTATUS, t0

/* Check if previous privilege mode by status.SPP */
Expand All @@ -755,12 +760,15 @@ FUNC thread_resume , :
csrw CSR_XSCRATCH, tp
2:
/* Restore all general-purpose registers */
load_xregs a0, THREAD_CTX_REG_RA, REG_RA, REG_TP
load_xregs a0, THREAD_CTX_REG_T0, REG_T0, REG_T2
load_xregs a0, THREAD_CTX_REG_S0, REG_S0, REG_S1
load_xregs a0, THREAD_CTX_REG_S2, REG_S2, REG_S11
load_xregs a0, THREAD_CTX_REG_T3, REG_T3, REG_T6
load_xregs a0, THREAD_CTX_REG_A0, REG_A0, REG_A7
load_xregs sp, THREAD_CTX_REG_RA, REG_RA
load_xregs sp, THREAD_CTX_REG_GP, REG_GP
load_xregs sp, THREAD_CTX_REG_TP, REG_TP
load_xregs sp, THREAD_CTX_REG_T0, REG_T0, REG_T2
load_xregs sp, THREAD_CTX_REG_S0, REG_S0, REG_S1
load_xregs sp, THREAD_CTX_REG_A0, REG_A0, REG_A7
load_xregs sp, THREAD_CTX_REG_S2, REG_S2, REG_S11
load_xregs sp, THREAD_CTX_REG_T3, REG_T3, REG_T6
load_xregs sp, THREAD_CTX_REG_SP, REG_SP /* sp must be last one */

XRET
END_FUNC thread_resume
Expand Down