Miscellaneous fixes and improvements for RISC-V #7043
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Instead of setting exception return PC into "ra" register and assign it to XEPC, we should directly set exception return PC into "XEPC" CSR to improve code redability. Signed-off-by: Alvin Chang <[email protected]> Reviewed-by: Yu Chien Peter Lin <[email protected]>
When the program wants to XRET to kernel mode, the value of XSCRATCH must be cleared to zero. Signed-off-by: Alvin Chang <[email protected]> Reviewed-by: Yu Chien Peter Lin <[email protected]>
Use sp as base register of load instructions can reduce code size if RVC
extension is enabled to generate 16-bit instructions. The following code
shows the difference after applying this commit.
Before:
f10009da: 0d053d83 ld s11,208(a0)
f10009de: 0c853d03 ld s10,200(a0)
f10009e2: 0c053c83 ld s9,192(a0)
f10009e6: 0b853c03 ld s8,184(a0)
f10009ea: 0b053b83 ld s7,176(a0)
f10009ee: 0a853b03 ld s6,168(a0)
f10009f2: 0a053a83 ld s5,160(a0)
f10009f6: 09853a03 ld s4,152(a0)
f10009fa: 09053983 ld s3,144(a0)
f10009fe: 08853903 ld s2,136(a0)
After:
f10009a6: 6dce ld s11,208(sp)
f10009a8: 6d2e ld s10,200(sp)
f10009aa: 6c8e ld s9,192(sp)
f10009ac: 7c6a ld s8,184(sp)
f10009ae: 7bca ld s7,176(sp)
f10009b0: 7b2a ld s6,168(sp)
f10009b2: 7a8a ld s5,160(sp)
f10009b4: 6a6a ld s4,152(sp)
f10009b6: 69ca ld s3,144(sp)
f10009b8: 692a ld s2,136(sp)
Signed-off-by: Alvin Chang <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
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removes redundant usage of "ra" register.
fixes the value of XSCRATCH when XRET to kernel mode.
uses "sp" as base register for load instructions to reduce the code size.