You can verilate 20x20 tile size eFPGA using Makefile under eFPGA_20x20/sim. It currently requires more than 45 GB system memory.

Or else, you can verilate less complex 10x10 tile size eFPGA using Makefile under eFPGA_10x10/sim. It currently requires more then 10 GB system memory with tracing all the units using --trace flag.

There are some warnings. They will be resolved.