Pinned Loading

1. UART_VIP UART_VIP Public

   Verification IP of fully parameterized two agents UART

   SystemVerilog 1

2. SPI_VIP SPI_VIP Public

   Verification IP of fully parameterized 4 modes SPI

   SystemVerilog 4

3. AXI-VIP AXI-VIP Public

   Verification IP of fully parameterized AXI4-Lite

   SystemVerilog

4. 16_bit_Risc_Machine 16_bit_Risc_Machine Public

   CENG Computer Organization Term Project

   HTML

5. Traffic_Conjuction_System Traffic_Conjuction_System Public

   CENG Digital Design Term Project

   C

6. eFPGA eFPGA Public

   Embedded FPGA with the size 20x20

   Verilog 1