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7. Misc. Hardware Stuff
This firmware is designed for the DAPHNE V2A hardware only. It cannot be used on DAPHNE V1 boards.
The front panel numbers the AFE ports 0 1 2 4 5 (left to right). The schematic/PCB numbers the AFE buses 0 4 3 2 1 This firmware now uses the front panel scheme, change made in the constraints file.
The programmable clock generator U18 should be configured to output the following clocks:
- CLK0 = 120.327MHz connects to MGT Quad 216, REFCLK0, pins F11/E11. Used for FELIX DAQ.
- CLK1 = 100MHz connects to bank 33, pins AA4/AB4. General purpose clock.
- CLK2 = 62.5MHz connects to bank 33, pins AA3/AA2. Currently unused.
- CLK3 = 125MHz connects to MGT Quad 213, REFCLK0, pins AA13/AB13. Used for GBE.
This firmware design uses the 100MHz system clock to generate the master clock and other internal clocks used by the firmware design.
The FPGA outputs a 62.5MHz clock on pins AF5/AF4. This clock goes to clock fanout buffer U20 and then copies of this clock go the 5 AFE chips.
Note that the OEICLK (125MHz for GbE operations) and DAQCLK (120.237MHz for output link sender logic) are generated from their respective GTP reference clock inputs. These clocks are generated by the MMCM/PLL contained in their respective GTP Quad modules.
If the clock generator U18 is ever re-configured by the microcontroller this can certainly affect the clocks going to the FPGA, and in that case the micro should hard reset the FPGA after the U18 output clocks are stable.
The front end alignment logic uses a number of different clocks and reset signals, so this sequencing is managed by a new module called clock_reset. The firmware design distinguishes between two different types of resets:
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A HARD RESET is an external signal controlled by the microcontroller. When asserted, the main MMCM/PLL in the FPGA is reset, and this momentarily disrupts all clocks output from this MMCM. After some time the MMCM returns to normal operation (locked=1) and then a state machine generates a sequence of reset pulses which are synchronized to various clock domains in the design.
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A SOFT RESET is generated by the user writing to a specific register in the GbE interface. When a soft reset is issued the main MMCM is not reset and all board clocks continue to run normally, and the reset signals are momentarily pulsed in their respective clock domains.
Normally a hard reset should not be needed. The FPGA should be programmed AFTER the microcontroller has initialized the clock generator U18. A soft reset is recommended after the FPGA is initialized, or any time the automatic front end logic reports bit errors in the framing pattern.
The DAPHNE2 board has a clock and data recovery (CDR) chip ADN2814CPZ U16. However this chip is no longer required in the new timing scheme and is effectively bypassed. The CLKOUT output of the CDR chip is ignored, and the DATAOUT output is the pulse width modulated clock which is used by the timing endpoint firmware in the FPGA. The LOL and LOS status bits are reported to the FPGA but not used by the new timing endpoint firmware.
The Gigabit Ethernet interface is FIBER and the SFP module connects to Quad 213, channel 0. The default IP and MAC address for this interface is determined by the byte value in the EFUSE register.
The FPGA contains a special one time programmable register called EFUSE. We use bits [15..8] of this register to store a unique value for each DAPHNE board. The EFUSE register is "burned" by using the Hardware Manager tool in Vivado and a JTAG cable is required for this operation.
The table below shows how this EFUSE byte value is used to determine the MAC, IP, and Timing Endpoint address:
Sticker EFUSE_USER[15..8] MAC_ADDR IP_ADDR (CERN) TIMING_ENDPOINT_ADDR
1 0x0B 00:80:55:DE:00:0B 10.73.137.104 0x000A
2 0x0C 00:80:55:DE:00:0C 10.73.137.105 0x000B
3 0x0D 00:80:55:DE:00:0D 10.73.137.110* 0x000C
4 0x0F 00:80:55:DE:00:0F 10.73.137.106 0x000E
5 0x0E 00:80:55:DE:00:0E 10.73.137.107 0x001D
6 0x10 00:80:55:DE:00:10 10.73.137.109 0x001F
7 0x11 00:80:55:DE:00:11 192.168.121.40 0x0020
8 0x12 00:80:55:DE:00:12 10.73.137.111 0x0021
9 0x13 00:80:55:DE:00:13 10.73.137.112 0x0022
10 0x14 00:80:55:DE:00:14 10.73.137.113 0x0023
11 0x15 00:80:55:DE:00:15 10.73.137.110* 0x0024
12 0x16 00:80:55:DE:00:16 10.73.137.110* 0x0025
* note this IP address has not been explicitly defined, this is the default value.
Quad 213 channel 0 is used for GbE. The FPGA can control the TX_DISABLE pin on this SFP. The FPGA can monitor the LOS and ABS signals on the SFP, as well as communicate with the SFP management interface (I2C).
Quad 216 is used for FELIX DAQ links. All four channels in this quad may be used. For FELIX generally only the MGT TX is used and the RX is disabled for each transceiver. The FPGA can control the TX_DISABLE, monitor the LOS and ABS signals, and communicate with the SFP management interface (I2C).
The FPGA firmware features and SPI slave that is used to communicate with the microcontroller. Two FIFOs are used to attach this slave SPI to the GbE interface. Command strings are written into the CMD FIFO (2k x 8). The command string must be less than 512 bytes ASCII data and terminated with 0x0d (CR) or 0x0a (LF). When the CMD FIFO has some data the SPI slave raises the SPI_IRQ line. The microcontroller then fetches the command string via the SPI interface, does the command, and writes any response string back to the SPI slave, which then stores it into the RES FIFO which can be read by the user through the GbE interface. If the user attempts to read an empty RES FIFO then 0xFF will be returned. This SPI interface between the FPGA and the microcontroller replaces the 100BASE-X Ethernet inteface on the microcontroller.
Also note that the DAPHNE microcontroller can hard reset the FPGA by pulling the RESETn line LOW momentarily. (There is a command to do this!)
The external interface trigger is now optically isolated. The input is 5-12VDC on an SMB connector (center positive). Note that the optoisolator device used on DAPHNE has an inverted output, so this inversion must be addressed in firmware.
There are 5 status LEDs. All are pulse stretched in the firmware so that momentary pulses are visible. The LED closest to the SFP Timing Interface connector is reserved for the microcontroller.
- uC LED: blinks at 1Hz when the microcontroller is programmed
- LED0: ON if the master clock MMCM is LOCKED
- LED1: ON if the automatic front end AFE alignment is done
- LED2: ON if the timing endpoint is locked and timestamp is valid
- LED3: ON if the GbE link is up and the speed is 1000
- LED4: ON if there is activity on the GbE link
- LED5: ON if there if the spy buffers are triggered (externally or internally via GbE)