1. Introduction
This firmware design is for the DAPHNE board, hardware revision 2A. It is designed to be built using Vivado 2022.x software from Xilinx. Whenever possible the binary output files will be attached as a ZIP file to each commit in the comments section.
- Automatic front end AFE data alignment, 40 channels.
- Updated timing endpoint
- Gigabit Ethernet port for slow controls and accessing the microcontroller
- Four output links to DAQ
- Streaming mode and self-triggered mode senders
- Spy buffers to capture input and output data
- Dynamic realtime input channel remapping
Throughout the sources there are various testbench files which are used to simulate firmware modules. There is no "top level" testbench that covers the entire design. Instead, subsections of the design are simulated and tested separately. For example, there is a testbench for a four input streaming sender, and another testbench for a single self triggered sender, and yet another for a group of ten self-triggered senderes.
The firmware MAY include a Xilinx "chipscope" Internal Logic Analyzer. See xilinx\output\probes.ltx for details.
This design is intended to be built in Vivado Non-Project mode. In a command line window cd to the src/xilinx directory and type:
vivado -mode tcl -source vivado_batch.tcl
After Vivado completes the output reports and bit/bin files should be located in the src/xilinx/output directory.
It is strongly recommended to NOT use the Vivado GUI ("project mode") to build this design; some settings in the tcl script will likely not be applied properly if that design flow is attempted. Also, the Vivado GUI sucks.
The timing constraints for this design were carefully written to provide complete timing coverage and also address the many different clock domains present in this design. After building the firmware be sure to look at the file src/xilinx/output/post_route_timing_summary.rpt and look for the text "All user specified timing constraints are met". If the design does not meet timing there will be negative slack in the worst case timing paths that will need to be addressed.
Output files including the BIN and BIT files, along with various reports, are usually ZIPPED up and attached to each commit in the comments section.
Some things to check and setup when using this firmware.
- Choose whether we are running with local clocks or using the timing endpoint (register 0x4001)
- Verify the clocks and timing endpoint is in a good state (registers 0x4000, 0x4002, 0x4003)
- Verify the AFE front end is aligned (spy buffers, 0x2000-0x2014)
- Set output record parameters (0x3000)
- For streaming mode senders, set/verify which inputs are used (0x5000-0x5027)
- Select which sender(s) are connected to which outputs (0x3001)
- For self-trigged sender, set the user threshold value (0x6000)